This post is closed. Problem is resolved by turning off SPI Debug message. In 2.6.34 Kernel config: (X:\lpc3250\ltib-qs\rpm\BUILD\linux-2.6.34\.config)
Change from CONFIG_SPI_DEBUG=y to: # CONFIG_SPI_DEBUG is not set After this, in #dmesg, we won't see those spi debugging message: .................. ssp-pl022 dev:ssp1: readwriter, rx: c3e0e006, rxend: c3e0e0dc, tx: 00000016, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e01a, rxend: c3e0e0dc, tx: 0000002a, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e02e, rxend: c3e0e0dc, tx: 0000003e, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e042, rxend: c3e0e0dc, tx: 00000052, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e056, rxend: c3e0e0dc, tx: 00000066, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e06a, rxend: c3e0e0dc, tx: 0000007a, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e07e, rxend: c3e0e0dc, tx: 0000008e, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e092, rxend: c3e0e0dc, tx: 000000a2, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e0a6, rxend: c3e0e0dc, tx: 000000b6, txend: 000000dc ssp-pl022 dev:ssp1: readwriter, rx: c3e0e0ba, rxend: c3e0e0dc, tx: 000000ca, txend: 000000dc .......................... However, we can get full 'spi data throughput'. Regards, Quentin On Mon, Aug 30, 2010 at 11:50 AM, Quentin YANG <[email protected]> wrote: > Hi, > > I am using transfer() function in spidev_test.c to verify the data > throughput on phytec LPC3250 board. > 2KBytes SPI message is sent out to SPI Slave device. > > There is a big delay (80us or so) after every 11 words transmission ( > 20 us or so, which is reasonable at 8MHz SPI Clock). > ==== I am wondering where is this significant delay coming from??? ====== > It largely reduced the SPI data througput. > It does not look like 'Linux Kernel Context switch'. > > See attached Timing Info on Scope. (TimingOnScope.txt) > > > SPI board setting is as follows (8MHZ spi clock, 16bit data size, > interrupt transfer) > > static struct pl022_config_chip spi1_chip_info = { > .lbm = LOOPBACK_DISABLED, > .com_mode = INTERRUPT_TRANSFER, > .iface = SSP_INTERFACE_MOTOROLA_SPI, > .hierarchy = SSP_MASTER, > .slave_tx_disable = 0, > .endian_tx = SSP_TX_LSB, > .endian_rx = SSP_RX_LSB, > .data_size = SSP_DATA_BITS_16, //SSP_DATA_BITS_8, > .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, > .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, > .clk_phase = SSP_CLK_FIRST_EDGE, //SSP_CLK_SECOND_EDGE, > .clk_pol = SSP_CLK_POL_IDLE_LOW, > .ctrl_len = SSP_BITS_8, > .wait_state = SSP_MWIRE_WAIT_ZERO, > .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, > .cs_control = phy3250_spi1_cs_set, > }; > > > Kernel (2.6.34) is using default 100ms context switch. ' CONFIG_HZ=100. ' > > Any help is appreciated. > > > Regards, > Quentin > ------------------------------------------------------------------------------ This SF.net Dev2Dev email is sponsored by: Show off your parallel programming skills. Enter the Intel(R) Threading Challenge 2010. http://p.sf.net/sfu/intel-thread-sfd _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
