On Tue, Aug 24, 2010 at 09:06:40AM +0900, Jassi Brar wrote: > On Tue, Aug 24, 2010 at 1:40 AM, Mark Brown > <[email protected]> wrote: > > When using PIO we have a timeout for the TX and RX FIFOs to ensure that > > the data actually gets transferred. Warn if we hit that timeout - it > > should never happen, but this makes sure we'll find out if it does. > > > > Signed-off-by: Mark Brown <[email protected]> > > --- > > drivers/spi/spi_s3c64xx.c | 6 ++++++ > > 1 files changed, 6 insertions(+), 0 deletions(-) > > > > diff --git a/drivers/spi/spi_s3c64xx.c b/drivers/spi/spi_s3c64xx.c > > index 7e627f7..f72e1c0 100644 > > --- a/drivers/spi/spi_s3c64xx.c > > +++ b/drivers/spi/spi_s3c64xx.c > > @@ -200,6 +200,9 @@ static void flush_fifo(struct s3c64xx_spi_driver_data > > *sdd) > > val = readl(regs + S3C64XX_SPI_STATUS); > > } while (TX_FIFO_LVL(val, sci) && loops--); > > > > + if (loops == 0) > > + dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); > > + > > /* Flush RxFIFO*/ > > loops = msecs_to_loops(1); > > do { > > @@ -210,6 +213,9 @@ static void flush_fifo(struct s3c64xx_spi_driver_data > > *sdd) > > break; > > } while (loops--); > > > > + if (loops == 0) > > + dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); > > + > > val = readl(regs + S3C64XX_SPI_CH_CFG); > > val &= ~S3C64XX_SPI_CH_SW_RST; > > writel(val, regs + S3C64XX_SPI_CH_CFG); > > Ok, though I'll be very surprised to see the FIFO flush failing. We > are not waiting > for data to be transferred, but for SW Reset to make its effect. > > Acked-by: Jassi Brar <[email protected]>
Applied, thanks. g. ------------------------------------------------------------------------------ This SF.net Dev2Dev email is sponsored by: Show off your parallel programming skills. Enter the Intel(R) Threading Challenge 2010. http://p.sf.net/sfu/intel-thread-sfd _______________________________________________ spi-devel-general mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/spi-devel-general
