Hi Grant,

> <phil.edwor...@renesas.com> wrote:
> > The driver attempts to read the received data immediately after
> > writing to the transmit buffer. If no data is available, the driver
> > currently waits 20ms until trying again. Since the hardware needs
> > to shift out the transmitted data, the first poll always fails,
> > leading to 20ms delay between bytes.
> >
> > This patch waits for the time it takes to transmit a byte before
> > reading the received data.
> >
> > Signed-off-by: Phil Edworthy <phil.edwor...@renesas.com>
> > ---
> > v2:
> >  Instead of replacing msleep(20) with udelay(1), this version now
> >  calculates the time it takes to shift out a byte, and uses udelay or
> >  ndelay for this time. After this it falls back to polling every 20ms
> >  using msleep. The delay has an empirical element based on testing at
> >  different speeds.
<snip>

> This is still just busywaiting. Which means just burning CPU cycles
> unconditionally even if it does finish early.
>
> Instead of doing nothing, it is actually a whole lot better to use a
> small delay and check if there is stuff to do frequently than it is to
> try and delay for the entire duration. Due to the way this driver is
> architected, nothing else can use the CPU during the delay().
>
> What would really be better is to load up the fifo and full as it will
> go and then rely on IRQs to tell the driver when it becomes ready to
> fill with more data.

Ok, I see now. I'll look at using dma instead though, as that will be better in 
the long run.

Thanks for your comments,
Phil
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