commit: a50eb1c7680973f5441ca20ac4da0af2055d0d87 From: Changhwan Youn <[email protected]> Date: Fri, 26 Nov 2010 13:21:53 +0900 Subject: [PATCH] ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register
This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb (ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register). Actually, S5PV310 has same cache controller(PL310). Following is from Catalin Marinas' commit. Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Signed-off-by: Changhwan Youn <[email protected]> Cc: <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Russell King <[email protected]> Signed-off-by: Kukjin Kim <[email protected]> --- arch/arm/mach-s5pv310/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index 82ce4aa..b2a37d0 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void) __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, S5P_VA_L2CC + L2X0_POWER_CTRL); - l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff); + l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); return 0; } _______________________________________________ stable mailing list [email protected] http://linux.kernel.org/mailman/listinfo/stable
