commit: 5b64aa72ead6f8be488d2be7af579f0d69fb7a6e
From: Rajkumar Manoharan <[email protected]>
Date: Thu, 27 Jan 2011 18:39:37 +0530
Subject: [PATCH] ath9k_hw: Fix system hang when resuming from S3/S4

The bit 6 & 7 of AR_WA (0x4004) should be enabled only
for the chips that are supporting L0s functionality
while resuming back from S3/S4.

Enabling these bits for AR9280 is causing system hang
within a few S3/S4-resume cycles.

Cc: [email protected]
Cc: Jack Lee <[email protected]>
Signed-off-by: Rajkumar Manoharan <[email protected]>
Signed-off-by: John W. Linville <[email protected]>
---
 drivers/net/wireless/ath/ath9k/ar9002_hw.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c 
b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index f8a7771..f44c84a 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -426,9 +426,8 @@ static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
                }
 
                /* WAR for ASPM system hang */
-               if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
+               if (AR_SREV_9285(ah) || AR_SREV_9287(ah))
                        val |= (AR_WA_BIT6 | AR_WA_BIT7);
-               }
 
                if (AR_SREV_9285E_20(ah))
                        val |= AR_WA_BIT23;

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