This is a note to let you know that I've just added the patch titled
ARM: smp_on_up: allow non-ARM SMP processors
to the 2.6.37-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-smp_on_up-allow-non-arm-smp-processors.patch
and it can be found in the queue-2.6.37 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From e98ff0f55a0232b578c9aa7f1c245868277ac7bc Mon Sep 17 00:00:00 2001
From: Russell King <[email protected]>
Date: Sun, 30 Jan 2011 16:40:20 +0000
Subject: ARM: smp_on_up: allow non-ARM SMP processors
From: Russell King <[email protected]>
commit e98ff0f55a0232b578c9aa7f1c245868277ac7bc upstream.
Allow non-ARM SMP processors to use the SMP_ON_UP feature. CPUs
supporting SMP must have the new CPU ID format, so check for this first.
Then check for ARM11MPCore, which fails the MPIDR check. Lastly check
the MPIDR reports multiprocessing extensions and that the CPU is part of
a multiprocessing system.
Reported-and-Tested-by: Stephen Boyd <[email protected]>
Acked-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm/kernel/head.S | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -392,24 +392,22 @@ ENDPROC(__turn_mmu_on)
#ifdef CONFIG_SMP_ON_UP
__fixup_smp:
- mov r4, #0x00070000
- orr r3, r4, #0xff000000 @ mask 0xff070000
- orr r4, r4, #0x41000000 @ val 0x41070000
- and r0, r9, r3
- teq r0, r4 @ ARM CPU and ARMv6/v7?
+ and r3, r9, #0x000f0000 @ architecture version
+ teq r3, #0x000f0000 @ CPU ID supported?
bne __fixup_smp_on_up @ no, assume UP
- orr r3, r3, #0x0000ff00
- orr r3, r3, #0x000000f0 @ mask 0xff07fff0
+ bic r3, r9, #0x00ff0000
+ bic r3, r3, #0x0000000f @ mask 0xff00fff0
+ mov r4, #0x41000000
orr r4, r4, #0x0000b000
- orr r4, r4, #0x00000020 @ val 0x4107b020
- and r0, r9, r3
- teq r0, r4 @ ARM 11MPCore?
+ orr r4, r4, #0x00000020 @ val 0x4100b020
+ teq r3, r4 @ ARM 11MPCore?
moveq pc, lr @ yes, assume SMP
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
- tst r0, #1 << 31
- movne pc, lr @ bit 31 => SMP
+ and r0, r0, #0xc0000000 @ multiprocessing extensions and
+ teq r0, #0x80000000 @ not part of a uniprocessor system?
+ moveq pc, lr @ yes, assume SMP
__fixup_smp_on_up:
adr r0, 1f
Patches currently in stable-queue which might be from
[email protected] are
queue-2.6.37/arm-smp_on_up-allow-non-arm-smp-processors.patch
queue-2.6.37/arm-smp-use-more-sane-register-allocation-for-__fixup_smp_on_up.patch
queue-2.6.37/arm-initrd-disable-initrd-if-passed-address-overlaps-reserved-region.patch
queue-2.6.37/arm-s5pv310-set-bit-22-in-the-pl310-cache-controller-auxctlr-register.patch
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