commit 58c5296991d233f2e492aa7a884635bba478cf12 upstream
There is an interoperability with AR9382/AR9380 in L1 state with a
few root complexes which can cause a hang. This is fixed by
setting some work around bits on the PCIE PHY. We fix by using
a new ini array to modify these bits when the radio is idle.
Cc: sta...@kernel.org
Cc: Jack Lee <jack....@atheros.com>
Cc: Carl Huang <carl.hu...@atheros.com>
Cc: David Quan <david.q...@atheros.com>
Cc: Nael Atallah <nael.atal...@atheros.com>
Cc: Sarvesh Shrivastava <sarvesh.shrivast...@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodrig...@atheros.com>
Signed-off-by: John W. Linville <linvi...@tuxdriver.com>
---
.../net/wireless/ath/ath9k/ar9003_2p2_initvals.h | 2 +-
drivers/net/wireless/ath/ath9k/ar9003_hw.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index a14a5e4..c655cd2 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -1842,7 +1842,7 @@ static const u32 ar9300_2p2_soc_preamble[][2] = {
static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
/* Addr allmodes */
- {0x00004040, 0x08212e5e},
+ {0x00004040, 0x0821265e},
{0x00004040, 0x0008003b},
{0x00004044, 0x00000000},
};
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index c2a0571..cd8e0bd 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -95,8 +95,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
/* Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
- ar9300PciePhy_clkreq_enable_L1_2p2,
- ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
+ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+ ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
2);
/* Fast clock modal settings */
--
1.7.4.15.g7811d
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