Currently, SPI clock modes are not set.
The clock setting is necessary to work well.
This patch supports a spi mode setup and bit order setup by IO control.
spi mode: mode 0 to mode 3
bit order: LSB first, MSB first
commit f258b44e22e07f5e98ac2260c70acff5784791b6
Kernel 3.2 3.3
Cc: [email protected]
Signed-off-by: Tomoya MORINAGA <[email protected]>
Signed-off-by: Grant Likely <[email protected]>
---
drivers/spi/spi-topcliff-pch.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 1e60827..0c4efed 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -1434,6 +1434,7 @@ static int __devinit pch_spi_pd_probe(struct
platform_device *plat_dev)
master->num_chipselect = PCH_MAX_CS;
master->setup = pch_spi_setup;
master->transfer = pch_spi_transfer;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
data->board_dat = board_dat;
data->plat_dev = plat_dev;
--
1.7.7.6
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