On Wed, 12 Nov 2014, Dave Airlie <[email protected]> wrote:
> From: Jani Nikula <[email protected]>
>
> original upstream commit: 7809a61176b385ebb3299ea43c58b1bb31ffb8c0
>
> Ivybridge + 30" monitor prints a drm error on every modeset, since IVB
> doesn't support DP3 we should even bother trying to use it.
>
> This regression has been introduced in
>
> commit 06ea66b6bb445043dc25a9626254d5c130093199
> Author: Todd Previte <[email protected]>
> Date: Mon Jan 20 10:19:39 2014 -0700
>
> drm/i915: Enable 5.4Ghz (HBR2) link rate for Displayport 1.2-capable
> devices
>
> Reported-by: Dave Airlie <[email protected]>
> Reference:
> http://mid.gmane.org/[email protected]
> Cc: Todd Previte <[email protected]>
> Cc: [email protected] (3.15+)
> Reviewed-by: Ville Syrjälä <[email protected]>
> Signed-off-by: Jani Nikula <[email protected]>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fdff1d4..59787f7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3347,9 +3347,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> }
> }
>
> - /* Training Pattern 3 support */
> + /* Training Pattern 3 support, both source and sink */
> if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
> - intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
> + intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
> + (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
I think you'll have to use IS_HASWELL(dev) and INTEL_INFO(dev) here for
stable kernels.
BR,
Jani.
> intel_dp->use_tps3 = true;
> DRM_DEBUG_KMS("Displayport TPS3 supported");
> } else
> --
> 1.9.3
>
--
Jani Nikula, Intel Open Source Technology Center
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