On 27/11/14 11:13, Markos Chandras wrote: > From: Leonid Yegoshin <[email protected]> > > There is a potential race when probing the TLB in TLBL/M/S exception > handlers for a matching entry. Between the time we hit a TLBL/S/M > exception and the time we get to execute the TLBP instruction, the
More specifically it is between the exception being triggered and the actual start of exception handling. HTW is disabled while at exception level so it isn't a problem after the handler has actually started. > HTW may have killed the TLB entry we are interested in hence the TLB maybe s/killed/replaced/ Sorry to be picky, but I think it's worth getting that wording as specific as possible for future reference. > probe may fail. However, in the existing handlers, we never checked the > status of the TLBP (ie check the result in the C0/Index register). We > fix this by adding such a check when the core implements the HTW. If > we couldn't find a matching entry, we return back and try again. > > Cc: <[email protected]> # v3.17+ > Signed-off-by: Leonid Yegoshin <[email protected]> > Signed-off-by: Markos Chandras <[email protected]> > --- > arch/mips/mm/tlbex.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c > index 7994368f96c4..3978a3d81366 100644 > --- a/arch/mips/mm/tlbex.c > +++ b/arch/mips/mm/tlbex.c > @@ -1872,8 +1872,16 @@ build_r4000_tlbchange_handler_head(u32 **p, struct > uasm_label **l, > uasm_l_smp_pgtable_change(l, *p); > #endif > iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ > - if (!m4kc_tlbp_war()) > + if (!m4kc_tlbp_war()) { > build_tlb_probe_entry(p); > + if (cpu_has_htw) { > + /* race condition happens, leaving */ How about expanding this comment a bit for people trying to figure out the code. Technically though: Reviewed-by: James Hogan <[email protected]> Thanks James > + uasm_i_ehb(p); > + uasm_i_mfc0(p, wr.r3, C0_INDEX); > + uasm_il_bltz(p, r, wr.r3, label_leave); > + uasm_i_nop(p); > + } > + } > return wr; > } > >
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