From: David Daney <[email protected]> This reverts commit 6575b1d4173eaeff6742a2c6dcbd835bb052952b.
It sets PG_IEC in cpu-probe. But this value is clobbered in tlb_init() so the system is never configured to take the RIXI specific exceptions. Caos ensues. Cc: <[email protected]> Signed-off-by: David Daney <[email protected]> --- arch/mips/include/asm/mipsregs.h | 1 - arch/mips/kernel/cpu-probe.c | 9 --------- 2 files changed, 10 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 5e4aef3..dfdca76 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -265,7 +265,6 @@ #define PG_XIE (_ULCAST_(1) << 30) #define PG_ELPA (_ULCAST_(1) << 29) #define PG_ESP (_ULCAST_(1) << 28) -#define PG_IEC (_ULCAST_(1) << 27) /* * R4x00 interrupt enable / cause bits diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5342674..63ace78 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -531,15 +531,6 @@ static void decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); - if (cpu_has_rixi) { - /* Enable the RIXI exceptions */ - write_c0_pagegrain(read_c0_pagegrain() | PG_IEC); - back_to_back_c0_hazard(); - /* Verify the IEC bit is set */ - if (read_c0_pagegrain() & PG_IEC) - c->options |= MIPS_CPU_RIXIEX; - } - #ifndef CONFIG_MIPS_CPS if (cpu_has_mips_r2) { c->core = get_ebase_cpunum(); -- 1.7.11.7 -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
