This is a note to let you know that I've just added the patch titled
ARM: DMA: ensure that old section mappings are flushed from the TLB
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-dma-ensure-that-old-section-mappings-are-flushed-from-the-tlb.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 6b076991dca9817e75c37e2f0db6d52611ea42fa Mon Sep 17 00:00:00 2001
From: Russell King <[email protected]>
Date: Thu, 17 Jul 2014 12:17:45 +0100
Subject: ARM: DMA: ensure that old section mappings are flushed from the TLB
From: Russell King <[email protected]>
commit 6b076991dca9817e75c37e2f0db6d52611ea42fa upstream.
When setting up the CMA region, we must ensure that the old section
mappings are flushed from the TLB before replacing them with page
tables, otherwise we can suffer from mismatched aliases if the CPU
speculatively prefetches from these mappings at an inopportune time.
A mismatched alias can occur when the TLB contains a section mapping,
but a subsequent prefetch causes it to load a page table mapping,
resulting in the possibility of the TLB containing two matching
mappings for the same virtual address region.
Acked-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Cc: Hou Pengyang <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm/mm/dma-mapping.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -429,12 +429,21 @@ void __init dma_contiguous_remap(void)
map.type = MT_MEMORY_DMA_READY;
/*
- * Clear previous low-memory mapping
+ * Clear previous low-memory mapping to ensure that the
+ * TLB does not see any conflicting entries, then flush
+ * the TLB of the old entries before creating new mappings.
+ *
+ * This ensures that any speculatively loaded TLB entries
+ * (even though they may be rare) can not cause any problems,
+ * and ensures that this code is architecturally compliant.
*/
for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
addr += PMD_SIZE)
pmd_clear(pmd_off_k(addr));
+ flush_tlb_kernel_range(__phys_to_virt(start),
+ __phys_to_virt(end));
+
iotable_init(&map, 1);
}
}
Patches currently in stable-queue which might be from
[email protected] are
queue-3.10/arm-dma-ensure-that-old-section-mappings-are-flushed-from-the-tlb.patch
queue-3.10/arm-8109-1-mm-modify-pte_write-and-pmd_write-logic-for-lpae.patch
queue-3.10/arm-7866-1-include-asm-use-long-long-instead-of-u64-within-atomic.h.patch
queue-3.10/arm-7829-1-add-.text.unlikely-and-.text.hot-to-arm-unwind-tables.patch
queue-3.10/arm-7931-1-correct-virt_addr_valid.patch
queue-3.10/arm-8108-1-mm-introduce-pte-pmd-_isset-and.patch
queue-3.10/arm-7867-1-include-asm-use-int-instead-of-unsigned-long-for-oldval-in-atomic_cmpxchg.patch
queue-3.10/arm-fix-asm-memory.h-build-error.patch
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