From: Ville Syrjälä <[email protected]> This patch has been added to the 3.18 stable tree. If you have any objections, please let us know.
=============== [ Upstream commit 8e7a65aa70bcc1235a44e40ae0da5056525fe081 ] We accidentally lost the initial DPLL register write in 1c4e02746147 drm/i915: Fix DVO 2x clock enable on 830M The "three times for luck" hack probably saved us from a total disaster. But anyway, bring the initial write back so that the code actually makes some sense. Reported-and-tested-by: Nick Bowler <[email protected]> References: http://mid.gmane.org/can_qmvymaarxygecvvsgvsmo7-6ohzr8hmf5vhkkl4i9kom...@mail.gmail.com Cc: [email protected] Cc: Nick Bowler <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Sasha Levin <[email protected]> --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 448327f..60c68e3c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1650,6 +1650,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); } + I915_WRITE(reg, dpll); + /* Wait for the clocks to stabilize. */ POSTING_READ(reg); udelay(150); -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
