This is a note to let you know that I've just added the patch titled
ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores
to the 3.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-7501-1-decompressor-reset-ttbcr-for-vmsa-armv7-cores.patch
and it can be found in the queue-3.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From dbece45894d3ab1baac15a96dc4e1e8e23f64a93 Mon Sep 17 00:00:00 2001
From: Will Deacon <[email protected]>
Date: Fri, 24 Aug 2012 15:20:59 +0100
Subject: ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores
From: Will Deacon <[email protected]>
commit dbece45894d3ab1baac15a96dc4e1e8e23f64a93 upstream.
When enabling the MMU for ARMv7 CPUs, the decompressor does not touch
the ttbcr register, assuming that it will be zeroed (N == 0, EAE == 0).
Given that only EAE is defined as 0 for non-secure copies of the
register (and a bootloader such as kexec may leave it set to 1 anyway),
we should ensure that we reset the register ourselves before turning on
the MMU.
This patch zeroes TTBCR.EAE and TTBCR.N prior to enabling the MMU for
ARMv7 cores in the decompressor, configuring us exclusively for 32-bit
translation tables via TTBR0.
Acked-by: Nicolas Pitre <[email protected]>
Signed-off-by: Matthew Leach <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm/boot/compressed/head.S | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -659,10 +659,14 @@ __armv7_mmu_cache_on:
#ifdef CONFIG_CPU_ENDIAN_BE8
orr r0, r0, #1 << 25 @ big-endian page tables
#endif
+ mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
orrne r0, r0, #1 @ MMU enabled
movne r1, #0xfffffffd @ domain 0 = client
+ bic r6, r6, #1 << 31 @ 32-bit translation system
+ bic r6, r6, #3 << 0 @ use only ttbr0
mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
+ mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
#endif
mcr p15, 0, r0, c7, c5, 4 @ ISB
mcr p15, 0, r0, c1, c0, 0 @ load control register
Patches currently in stable-queue which might be from [email protected] are
queue-3.5/arm-7527-1-uaccess-explicitly-check-__user-pointer-when-cpu_use_domains.patch
queue-3.5/arm-7526-1-traps-send-sigill-if-get_user-fails-on-undef-handling-path.patch
queue-3.5/arm-7496-1-hw_breakpoint-don-t-rely-on-dfsr-to-show-watchpoint-access-type.patch
queue-3.5/arm-7501-1-decompressor-reset-ttbcr-for-vmsa-armv7-cores.patch
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