commit: e1e5b7e4251c7538ca08c2c5545b0c2fbd8a6635 From: Matthew Leach <[email protected]> Date: Tue, 11 Sep 2012 17:56:57 +0100 Subject: ARM: 7532/1: decompressor: reset SCTLR.TRE for VMSA ARMv7 cores
This patch zeroes the SCTLR.TRE bit prior to setting the mapping as cacheable for ARMv7 cores in the decompressor, ensuring that the memory region attributes are obtained from the C and B bits, not from the page tables. Cc: Nicolas Pitre <[email protected]> Reviewed-by: Will Deacon <[email protected]> Signed-off-by: Matthew Leach <[email protected]> Signed-off-by: Will Deacon <[email protected]> Cc: <[email protected]> Signed-off-by: Russell King <[email protected]> --- arch/arm/boot/compressed/head.S | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 81769c1..bc67cbf 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -653,6 +653,7 @@ __armv7_mmu_cache_on: mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs #endif mrc p15, 0, r0, c1, c0, 0 @ read control reg + bic r0, r0, #1 << 28 @ clear SCTLR.TRE orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer #ifdef CONFIG_MMU -- 1.7.3.4 -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
