This is a note to let you know that I've just added the patch titled
drm/i915: enable lvds pin pairs before dpll on gen2
to the 3.5-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-enable-lvds-pin-pairs-before-dpll-on-gen2.patch
and it can be found in the queue-3.5 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 5b5896e4e1f353ef3dbc4e4e9ee44d53ccf105d7 Mon Sep 17 00:00:00 2001
From: Daniel Vetter <[email protected]>
Date: Tue, 11 Sep 2012 12:37:55 +0200
Subject: drm/i915: enable lvds pin pairs before dpll on gen2
From: Daniel Vetter <[email protected]>
commit 5b5896e4e1f353ef3dbc4e4e9ee44d53ccf105d7 upstream.
Otherwise things migt not work too well.
Breakage introduced in
commit eb1cbe4848b01f9f073064377875bc7d71eb401b
Author: Daniel Vetter <[email protected]>
Date: Wed Mar 28 23:12:16 2012 +0200
drm/i915: split PLL update code out of i9xx_crtc_mode_set
Reviewed-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3926,12 +3926,6 @@ static void i8xx_update_pll(struct drm_c
POSTING_READ(DPLL(pipe));
udelay(150);
- I915_WRITE(DPLL(pipe), dpll);
-
- /* Wait for the clocks to stabilize. */
- POSTING_READ(DPLL(pipe));
- udelay(150);
-
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
* This is an exception to the general rule that mode_set doesn't turn
* things on.
@@ -3939,6 +3933,12 @@ static void i8xx_update_pll(struct drm_c
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
intel_update_lvds(crtc, clock, adjusted_mode);
+ I915_WRITE(DPLL(pipe), dpll);
+
+ /* Wait for the clocks to stabilize. */
+ POSTING_READ(DPLL(pipe));
+ udelay(150);
+
/* The pixel multiplier can only be updated once the
* DPLL is enabled and the clocks are stable.
*
Patches currently in stable-queue which might be from [email protected] are
queue-3.5/drm-i915-hdmi-clear-audio-enable-bit-for-hot-plug.patch
queue-3.5/drm-i915-extract-connector-update-from-intel_ddc_get_modes-for-reuse.patch
queue-3.5/drm-i915-use-hsw-rps-tuning-values-everywhere-on-gen6.patch
queue-3.5/drm-i915-fall-back-to-bit-banging-if-gmbus-fails-in-crt-edid-reads.patch
queue-3.5/drm-i915-enable-lvds-pin-pairs-before-dpll-on-gen2.patch
queue-3.5/drm-i915-set-the-right-gen3-flip_done-mode-also-at-resume.patch
queue-3.5/drm-i915-reduce-a-pin-leak-bug-into-a-warn.patch
queue-3.5/drm-i915-fix-wrong-order-of-parameters-in-port-checking.patch
--
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