This is a note to let you know that I've just added the patch titled
ARM: 7606/1: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs
to the 3.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-7606-1-cache-flush-to-louu-instead-of-louis-on-uniprocessor-cpus.patch
and it can be found in the queue-3.7 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From d056a699dd3d9366dd3b4d9996e7848209199cda Mon Sep 17 00:00:00 2001
From: Will Deacon <[email protected]>
Date: Wed, 19 Dec 2012 15:01:08 +0100
Subject: ARM: 7606/1: cache: flush to LoUU instead of LoUIS on uniprocessor CPUs
From: Will Deacon <[email protected]>
commit d056a699dd3d9366dd3b4d9996e7848209199cda upstream.
flush_cache_louis flushes the D-side caches to the point of unification
inner-shareable. On uniprocessor CPUs, this is defined as zero and
therefore no flushing will take place. Rather than invent a new interface
for UP systems, instead use our SMP_ON_UP patching code to read the
LoUU from the CLIDR instead.
Cc: Lorenzo Pieralisi <[email protected]>
Tested-by: Guennadi Liakhovetski <[email protected]>
Signed-off-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm/mm/cache-v7.S | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all)
ENTRY(v7_flush_dcache_louis)
dmb @ ensure ordering with previous
memory accesses
mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
- ands r3, r0, #0xe00000 @ extract LoUIS from clidr
- mov r3, r3, lsr #20 @ r3 = LoUIS * 2
+ ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
+ ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
+ ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
+ ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
moveq pc, lr @ return if level == 0
mov r10, #0 @ r10 (starting level) = 0
b flush_levels @ start flushing cache levels
Patches currently in stable-queue which might be from [email protected] are
queue-3.7/arm-7606-1-cache-flush-to-louu-instead-of-louis-on-uniprocessor-cpus.patch
queue-3.7/arm-7607-1-realview-fix-private-peripheral-memory-base-for-eb-rev.-b-boards.patch
queue-3.7/mm-highmem-export-kmap_to_page-for-modules.patch
queue-3.7/arm64-signal-push-the-unwinding-prologue-on-the-signal-stack.patch
queue-3.7/virtio-9p-correctly-pass-physical-address-to-userspace-for-high-pages.patch
queue-3.7/virtio-force-vring-descriptors-to-be-allocated-from-lowmem.patch
queue-3.7/arm64-compat-for-clock_adjtime-2-is-miswired.patch
queue-3.7/arm-mm-use-pteval_t-to-represent-page-protection-values.patch
--
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