This is a note to let you know that I've just added the patch titled
drm/nouveau/clock: fix support for more than 2 monitors on nve0
to the 3.7-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-nouveau-clock-fix-support-for-more-than-2-monitors-on-nve0.patch
and it can be found in the queue-3.7 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From d19528a9e4f220519c2cb3f56ef0c84ead3ee440 Mon Sep 17 00:00:00 2001
From: Aleksi Torhamo <[email protected]>
Date: Fri, 4 Jan 2013 18:39:13 +0200
Subject: drm/nouveau/clock: fix support for more than 2 monitors on nve0
From: Aleksi Torhamo <[email protected]>
commit d19528a9e4f220519c2cb3f56ef0c84ead3ee440 upstream.
Fixes regression introduced in commit 70790f4f
"drm/nouveau/clock: pull in the implementation from all over the place"
When code was moved from nv50_crtc_set_clock to nvc0_clock_pll_set,
the PLLs it is used for got limited to only the first two VPLLs.
nv50_crtc_set_clock was only called to change VPLLs, so it didn't
limit what it was used for in any way. Since nvc0_clock_pll_set is
used for all PLLs, it has to specify which PLLs the code is used for,
and only listed the first two VPLLs.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=58735
This patch is a -stable candidate for 3.7.
Signed-off-by: Aleksi Torhamo <[email protected]>
Tested-by: Aleksi Torhamo <[email protected]>
Tested-by: Sean Santos <[email protected]>
Signed-off-by: Ben Skeggs <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h | 2 ++
drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c | 2 ++
2 files changed, 4 insertions(+)
--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h
@@ -38,6 +38,8 @@ enum nvbios_pll_type {
PLL_UNK42 = 0x42,
PLL_VPLL0 = 0x80,
PLL_VPLL1 = 0x81,
+ PLL_VPLL2 = 0x82,
+ PLL_VPLL3 = 0x83,
PLL_MAX = 0xff
};
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
@@ -52,6 +52,8 @@ nvc0_clock_pll_set(struct nouveau_clock
switch (info.type) {
case PLL_VPLL0:
case PLL_VPLL1:
+ case PLL_VPLL2:
+ case PLL_VPLL3:
nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
nv_wr32(priv, info.reg + 0x10, fN << 16);
Patches currently in stable-queue which might be from [email protected] are
queue-3.7/drm-nvc0-fb-fix-crash-when-different-mutex-is-used-to-protect-same-list.patch
queue-3.7/drm-nouveau-clock-fix-support-for-more-than-2-monitors-on-nve0.patch
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