enable handling of separate mask registers for Orion SoC GPIOs, fixing indeed the regression introduced by e59347a "arm: orion: Use generic irq chip".
Reported-by: Joey Oravec <[email protected]> Signed-off-by: Gerlando Falauto <[email protected]> Tested-by: Simon Guinot <[email protected]> --- Changes from v3: SOB line --- arch/arm/plat-orion/gpio.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index c29ee7e..a4dc04a 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -522,7 +522,8 @@ void __init orion_gpio_init(struct device_node *np, ct->handler = handle_edge_irq; ct->chip.name = ochip->chip.label; - irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, + irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE | + IRQ_GC_SEPARATE_MASK_REGISTERS, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); /* Setup irq domain on top of the generic chip. */ -- 1.7.10.1 -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
