This is a note to let you know that I've just added the patch titled
drm/radeon/dce6: add missing display reg for tiling setup
to the 3.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-radeon-dce6-add-missing-display-reg-for-tiling-setup.patch
and it can be found in the queue-3.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 7c1c7c18fc752b2a1d07597286467ef186312463 Mon Sep 17 00:00:00 2001
From: Alex Deucher <[email protected]>
Date: Fri, 5 Apr 2013 10:28:08 -0400
Subject: drm/radeon/dce6: add missing display reg for tiling setup
From: Alex Deucher <[email protected]>
commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream.
A new tiling config register for the display blocks was
added on DCE6.
May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=62889
https://bugs.freedesktop.org/show_bug.cgi?id=57919
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/radeon/ni.c | 2 ++
drivers/gpu/drm/radeon/nid.h | 4 ++++
drivers/gpu/drm/radeon/si.c | 1 +
drivers/gpu/drm/radeon/sid.h | 2 ++
4 files changed, 9 insertions(+)
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -621,6 +621,8 @@ static void cayman_gpu_init(struct radeo
WREG32(GB_ADDR_CONFIG, gb_addr_config);
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+ if (ASIC_IS_DCE6(rdev))
+ WREG32(DMIF_ADDR_CALC, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -45,6 +45,10 @@
#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
#define DMIF_ADDR_CONFIG 0xBD4
+
+/* DCE6 only */
+#define DMIF_ADDR_CALC 0xC00
+
#define SRBM_GFX_CNTL 0x0E44
#define RINGID(x) (((x) &
0x3) << 0)
#define VMID(x) (((x) &
0x7) << 0)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1765,6 +1765,7 @@ static void si_gpu_init(struct radeon_de
WREG32(GB_ADDR_CONFIG, gb_addr_config);
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMIF_ADDR_CALC, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -65,6 +65,8 @@
#define DMIF_ADDR_CONFIG 0xBD4
+#define DMIF_ADDR_CALC 0xC00
+
#define SRBM_STATUS 0xE50
#define GRBM_RQ_PENDING (1 << 5)
#define VMC_BUSY (1 << 8)
Patches currently in stable-queue which might be from [email protected]
are
queue-3.9/drm-radeon-fix-typo-in-rv515_mc_resume.patch
queue-3.9/drm-radeon-update-wait_for_vblank-for-evergreen.patch
queue-3.9/drm-radeon-add-some-new-si-pci-ids.patch
queue-3.9/drm-radeon-dce6-add-missing-display-reg-for-tiling-setup.patch
queue-3.9/drm-radeon-don-t-use-get_engine_clock-on-apus.patch
queue-3.9/drm-radeon-update-wait_for_vblank-for-r5xx-r7xx.patch
queue-3.9/drm-radeon-properly-lock-disp-in-mc_stop-resume-for-r5xx-r7xx.patch
queue-3.9/drm-radeon-update-wait_for_vblank-for-r1xx-r4xx.patch
queue-3.9/drm-radeon-disable-the-crtcs-in-mc_stop-evergreen-v2.patch
queue-3.9/drm-radeon-use-frac-fb-div-on-rs780-rs880.patch
queue-3.9/drm-radeon-properly-lock-disp-in-mc_stop-resume-for-evergreen.patch
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