This is a note to let you know that I've just added the patch titled
arm64: mm: Fix operands of clz in __flush_dcache_all
to the 3.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-mm-fix-operands-of-clz-in-__flush_dcache_all.patch
and it can be found in the queue-3.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From b4fed0796841b5293b9c9427a5391b7bb20ef2d9 Mon Sep 17 00:00:00 2001
From: Sukanto Ghosh <[email protected]>
Date: Tue, 14 May 2013 10:26:54 +0100
Subject: arm64: mm: Fix operands of clz in __flush_dcache_all
From: Sukanto Ghosh <[email protected]>
commit b4fed0796841b5293b9c9427a5391b7bb20ef2d9 upstream.
The format of the lower 32-bits of the 64-bit operand to 'dc cisw' is
unchanged from ARMv7 architecture and the upper bits are RES0. This
implies that the 'way' field of the operand of 'dc cisw' occupies the
bit-positions [31 .. (32-A)]. Due to the use of 64-bit extended operands
to 'clz', the existing implementation of __flush_dcache_all is incorrectly
placing the 'way' field in the bit-positions [63 .. (64-A)].
Signed-off-by: Sukanto Ghosh <[email protected]>
Tested-by: Anup Patel <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm64/mm/cache.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -52,7 +52,7 @@ loop1:
add x2, x2, #4 // add 4 (line length offset)
mov x4, #0x3ff
and x4, x4, x1, lsr #3 // find maximum number on the
way size
- clz x5, x4 // find bit position of way
size increment
+ clz w5, w4 // find bit position of way
size increment
mov x7, #0x7fff
and x7, x7, x1, lsr #13 // extract max number of the
index size
loop2:
Patches currently in stable-queue which might be from [email protected] are
queue-3.9/arm64-mm-fix-operands-of-clz-in-__flush_dcache_all.patch
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