This is a note to let you know that I've just added the patch titled
powerpc/perf: Freeze PMC5/6 if we're not using them
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-perf-freeze-pmc5-6-if-we-re-not-using-them.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 7a7a41f9d5b28ac3a916b057a7d3cd3f435ee9a6 Mon Sep 17 00:00:00 2001
From: Michael Ellerman <[email protected]>
Date: Fri, 28 Jun 2013 18:15:12 +1000
Subject: powerpc/perf: Freeze PMC5/6 if we're not using them
From: Michael Ellerman <[email protected]>
commit 7a7a41f9d5b28ac3a916b057a7d3cd3f435ee9a6 upstream.
On Power8 we can freeze PMC5 and 6 if we're not using them. Normally they
run all the time.
As noticed by Anshuman, we should unfreeze them when we disable the PMU
as there are legacy tools which expect them to run all the time.
Signed-off-by: Michael Ellerman <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/perf/core-book3s.c | 5 +++--
arch/powerpc/perf/power8-pmu.c | 4 ++++
3 files changed, 8 insertions(+), 2 deletions(-)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -626,6 +626,7 @@
#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred,
set to 0 after handling exception */
#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads
*/
+#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -75,6 +75,7 @@ static unsigned int freeze_events_kernel
#define MMCR0_FCHV 0
#define MMCR0_PMCjCE MMCR0_PMCnCE
+#define MMCR0_FC56 0
#define MMCR0_PMAO 0
#define SPRN_MMCRA SPRN_MMCR2
@@ -870,11 +871,11 @@ static void power_pmu_disable(struct pmu
}
/*
- * Set the 'freeze counters' bit, clear PMAO.
+ * Set the 'freeze counters' bit, clear PMAO/FC56.
*/
val = mfspr(SPRN_MMCR0);
val |= MMCR0_FC;
- val &= ~MMCR0_PMAO;
+ val &= ~(MMCR0_PMAO | MMCR0_FC56);
/*
* The barrier is to make sure the mtspr has been
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -391,6 +391,10 @@ static int power8_compute_mmcr(u64 event
if (pmc_inuse & 0x7c)
mmcr[0] |= MMCR0_PMCjCE;
+ /* If we're not using PMC 5 or 6, freeze them */
+ if (!(pmc_inuse & 0x60))
+ mmcr[0] |= MMCR0_FC56;
+
mmcr[1] = mmcr1;
mmcr[2] = mmcra;
Patches currently in stable-queue which might be from [email protected] are
queue-3.10/powerpc-perf-don-t-enable-if-we-have-zero-events.patch
queue-3.10/powerpc-rename-and-flesh-out-the-facility-unavailable-exception-handler.patch
queue-3.10/powerpc-perf-check-that-events-only-include-valid-bits-on-power8.patch
queue-3.10/powerpc-wire-up-the-hv-facility-unavailable-exception.patch
queue-3.10/powerpc-remove-kvmtest-from-relon-exception-handlers.patch
queue-3.10/powerpc-perf-rework-disable-logic-in-pmu_disable.patch
queue-3.10/powerpc-remove-unreachable-relocation-on-exception-handlers.patch
queue-3.10/powerpc-perf-freeze-pmc5-6-if-we-re-not-using-them.patch
queue-3.10/powerpc-perf-use-existing-out-label-in-power_pmu_enable.patch
--
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