This is a note to let you know that I've just added the patch titled
powerpc/perf: Rework disable logic in pmu_disable()
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-perf-rework-disable-logic-in-pmu_disable.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 378a6ee99e4a431ec84e4e61893445c041c93007 Mon Sep 17 00:00:00 2001
From: Michael Ellerman <[email protected]>
Date: Fri, 28 Jun 2013 18:15:11 +1000
Subject: powerpc/perf: Rework disable logic in pmu_disable()
From: Michael Ellerman <[email protected]>
commit 378a6ee99e4a431ec84e4e61893445c041c93007 upstream.
In pmu_disable() we disable the PMU by setting the FC (Freeze Counters)
bit in MMCR0. In order to do this we have to read/modify/write MMCR0.
It's possible that we read a value from MMCR0 which has PMAO (PMU Alert
Occurred) set. When we write that value back it will cause an interrupt
to occur. We will then end up in the PMU interrupt handler even though
we are supposed to have just disabled the PMU.
We can avoid this by making sure we never write PMAO back. We should not
lose interrupts because when the PMU is re-enabled the overflowed values
will cause another interrupt.
We also reorder the clearing of SAMPLE_ENABLE so that is done after the
PMU is frozen. Otherwise there is a small window between the clearing of
SAMPLE_ENABLE and the setting of FC where we could take an interrupt and
incorrectly see SAMPLE_ENABLE not set. This would for example change the
logic in perf_read_regs().
Signed-off-by: Michael Ellerman <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/powerpc/perf/core-book3s.c | 31 +++++++++++++++++++------------
1 file changed, 19 insertions(+), 12 deletions(-)
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -75,6 +75,7 @@ static unsigned int freeze_events_kernel
#define MMCR0_FCHV 0
#define MMCR0_PMCjCE MMCR0_PMCnCE
+#define MMCR0_PMAO 0
#define SPRN_MMCRA SPRN_MMCR2
#define MMCRA_SAMPLE_ENABLE 0
@@ -852,7 +853,7 @@ static void write_mmcr0(struct cpu_hw_ev
static void power_pmu_disable(struct pmu *pmu)
{
struct cpu_hw_events *cpuhw;
- unsigned long flags;
+ unsigned long flags, val;
if (!ppmu)
return;
@@ -860,9 +861,6 @@ static void power_pmu_disable(struct pmu
cpuhw = &__get_cpu_var(cpu_hw_events);
if (!cpuhw->disabled) {
- cpuhw->disabled = 1;
- cpuhw->n_added = 0;
-
/*
* Check if we ever enabled the PMU on this cpu.
*/
@@ -872,6 +870,21 @@ static void power_pmu_disable(struct pmu
}
/*
+ * Set the 'freeze counters' bit, clear PMAO.
+ */
+ val = mfspr(SPRN_MMCR0);
+ val |= MMCR0_FC;
+ val &= ~MMCR0_PMAO;
+
+ /*
+ * The barrier is to make sure the mtspr has been
+ * executed and the PMU has frozen the events etc.
+ * before we return.
+ */
+ write_mmcr0(cpuhw, val);
+ mb();
+
+ /*
* Disable instruction sampling if it was enabled
*/
if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
@@ -880,14 +893,8 @@ static void power_pmu_disable(struct pmu
mb();
}
- /*
- * Set the 'freeze counters' bit.
- * The barrier is to make sure the mtspr has been
- * executed and the PMU has frozen the events
- * before we return.
- */
- write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
- mb();
+ cpuhw->disabled = 1;
+ cpuhw->n_added = 0;
}
local_irq_restore(flags);
}
Patches currently in stable-queue which might be from [email protected] are
queue-3.10/powerpc-perf-don-t-enable-if-we-have-zero-events.patch
queue-3.10/powerpc-rename-and-flesh-out-the-facility-unavailable-exception-handler.patch
queue-3.10/powerpc-perf-check-that-events-only-include-valid-bits-on-power8.patch
queue-3.10/powerpc-wire-up-the-hv-facility-unavailable-exception.patch
queue-3.10/powerpc-remove-kvmtest-from-relon-exception-handlers.patch
queue-3.10/powerpc-perf-rework-disable-logic-in-pmu_disable.patch
queue-3.10/powerpc-remove-unreachable-relocation-on-exception-handlers.patch
queue-3.10/powerpc-perf-freeze-pmc5-6-if-we-re-not-using-them.patch
queue-3.10/powerpc-perf-use-existing-out-label-in-power_pmu_enable.patch
--
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