This is a note to let you know that I've just added the patch titled
ARM: KVM: add missing dsb before invalidating Stage-2 TLBs
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-kvm-add-missing-dsb-before-invalidating-stage-2-tlbs.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 479c5ae2f8a55509b691494cd13691d3dc31d102 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <[email protected]>
Date: Fri, 21 Jun 2013 13:08:47 +0100
Subject: ARM: KVM: add missing dsb before invalidating Stage-2 TLBs
From: Marc Zyngier <[email protected]>
commit 479c5ae2f8a55509b691494cd13691d3dc31d102 upstream.
When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.
For this purpose, add a dsb instruction to __kvm_tlb_flush_vmid_ipa
before doing the TLB invalidation itself.
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
Signed-off-by: Jonghwan Choi <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm/kvm/interrupts.S | 1 +
1 file changed, 1 insertion(+)
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -49,6 +49,7 @@ __kvm_hyp_code_start:
ENTRY(__kvm_tlb_flush_vmid_ipa)
push {r2, r3}
+ dsb ishst
add r0, r0, #KVM_VTTBR
ldrd r2, r3, [r0]
mcrr p15, 6, r2, r3, c2 @ Write VTTBR
Patches currently in stable-queue which might be from [email protected] are
queue-3.10/arm-kvm-clear-exclusive-monitor-on-all-exception-returns.patch
queue-3.10/arm-kvm-add-missing-dsb-before-invalidating-stage-2-tlbs.patch
queue-3.10/arm-kvm-perform-save-restore-of-par.patch
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