This is a note to let you know that I've just added the patch titled
arm64: Only enable local interrupts after the CPU is marked online
to the 3.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-only-enable-local-interrupts-after-the-cpu-is-marked-online.patch
and it can be found in the queue-3.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 53ae3acd4390ffeecb3a11dbd5be347b5a3d98f2 Mon Sep 17 00:00:00 2001
From: Catalin Marinas <[email protected]>
Date: Fri, 19 Jul 2013 15:08:15 +0100
Subject: arm64: Only enable local interrupts after the CPU is marked online
From: Catalin Marinas <[email protected]>
commit 53ae3acd4390ffeecb3a11dbd5be347b5a3d98f2 upstream.
There is a slight chance that (timer) interrupts are triggered before a
secondary CPU has been marked online with implications on softirq thread
affinity.
Signed-off-by: Catalin Marinas <[email protected]>
Reported-by: Kirill Tkhai <[email protected]>
Cc: Mark Brown <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
arch/arm64/kernel/smp.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -200,13 +200,6 @@ asmlinkage void __cpuinit secondary_star
raw_spin_unlock(&boot_lock);
/*
- * Enable local interrupts.
- */
- notify_cpu_starting(cpu);
- local_irq_enable();
- local_fiq_enable();
-
- /*
* OK, now it's safe to let the boot CPU continue. Wait for
* the CPU migration code to notice that the CPU is online
* before we continue.
@@ -215,6 +208,14 @@ asmlinkage void __cpuinit secondary_star
complete(&cpu_running);
/*
+ * Enable GIC and timers.
+ */
+ notify_cpu_starting(cpu);
+
+ local_irq_enable();
+ local_fiq_enable();
+
+ /*
* OK, it's off to the idle thread for us
*/
cpu_startup_entry(CPUHP_ONLINE);
Patches currently in stable-queue which might be from [email protected]
are
queue-3.10/arm64-dts-reserve-the-memory-used-for-secondary-cpu-release-address.patch
queue-3.10/arm64-only-enable-local-interrupts-after-the-cpu-is-marked-online.patch
queue-3.10/arm64-virt-ensure-visibility-of-__boot_cpu_mode.patch
queue-3.10/arm64-change-kernel-stack-size-to-16k.patch
queue-3.10/arm64-use-normal-noncacheable-memory-for-writecombine.patch
queue-3.10/arm64-fix-possible-invalid-fpsimd-initialization-state.patch
queue-3.10/arm64-check-for-number-of-arguments-in-syscall_get-set_arguments.patch
queue-3.10/arm64-remove-unused-cpu_name-ascii-in-arch-arm64-mm-proc.s.patch
queue-3.10/clocksource-arch_timer-use-virtual-counters.patch
queue-3.10/arm64-ptrace-avoid-using-hw_breakpoint_empty-for-disabled-events.patch
queue-3.10/arm64-avoid-cache-flushing-in-flush_dcache_page.patch
queue-3.10/arm64-spinlock-retry-trylock-operation-if-strex-fails-on-free-lock.patch
queue-3.10/arm64-do-not-flush-the-d-cache-for-anonymous-pages.patch
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