This is a note to let you know that I've just added the patch titled
drm/radeon: disable pll sharing for DP on DCE4.1
to the 3.13-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-radeon-disable-pll-sharing-for-dp-on-dce4.1.patch
and it can be found in the queue-3.13 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 9ef4e1d000a5b335fcebfcf8aef3405e59574c89 Mon Sep 17 00:00:00 2001
From: Alex Deucher <[email protected]>
Date: Tue, 25 Feb 2014 10:21:43 -0500
Subject: drm/radeon: disable pll sharing for DP on DCE4.1
From: Alex Deucher <[email protected]>
commit 9ef4e1d000a5b335fcebfcf8aef3405e59574c89 upstream.
Causes display problems. We had already disabled
sharing for non-DP displays.
Based on a patch from:
Niels Ole Salscheider <[email protected]>
bug:
https://bugzilla.kernel.org/show_bug.cgi?id=58121
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/radeon/atombios_crtc.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1767,6 +1767,20 @@ static int radeon_atom_pick_pll(struct d
return ATOM_PPLL1;
DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID;
+ } else if (ASIC_IS_DCE41(rdev)) {
+ /* Don't share PLLs on DCE4.1 chips */
+ if
(ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
+ if (rdev->clock.dp_extclk)
+ /* skip PPLL programming if using ext clock */
+ return ATOM_PPLL_INVALID;
+ }
+ pll_in_use = radeon_get_pll_use_mask(crtc);
+ if (!(pll_in_use & (1 << ATOM_PPLL1)))
+ return ATOM_PPLL1;
+ if (!(pll_in_use & (1 << ATOM_PPLL2)))
+ return ATOM_PPLL2;
+ DRM_ERROR("unable to allocate a PPLL\n");
+ return ATOM_PPLL_INVALID;
} else if (ASIC_IS_DCE4(rdev)) {
/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or
ext clock,
* depending on the asic:
@@ -1794,7 +1808,7 @@ static int radeon_atom_pick_pll(struct d
if (pll != ATOM_PPLL_INVALID)
return pll;
}
- } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on
DCE4.1 chips */
+ } else {
/* use the same PPLL for all monitors with the same
clock */
pll = radeon_get_shared_nondp_ppll(crtc);
if (pll != ATOM_PPLL_INVALID)
Patches currently in stable-queue which might be from [email protected]
are
queue-3.13/drm-radeon-print-the-supported-atpx-function-mask.patch
queue-3.13/drm-radeon-fix-audio-disable-on-dce6.patch
queue-3.13/drm-radeon-disable-pll-sharing-for-dp-on-dce4.1.patch
queue-3.13/drm-radeon-fix-display-tiling-setup-on-si.patch
queue-3.13/drm-radeon-fix-missing-bo-reservation.patch
queue-3.13/drm-radeon-ni-fix-typo-in-dpm-sq-ramping-setup.patch
queue-3.13/drm-radeon-fix-cp-semaphores-on-cik.patch
queue-3.13/drm-radeon-free-uvd-ring-on-unload.patch
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