This is a note to let you know that I've just added the patch titled
drm/i915: Workaround incoherence between fences and LLC across multiple CPUs
to the 3.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-workaround-incoherence-between-fences-and-llc-across-multiple-cpus.patch
and it can be found in the queue-3.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From 0bdb6ae5a6447214693e9de94df3611cea80357a Mon Sep 17 00:00:00 2001
From: Chris Wilson <[email protected]>
Date: Thu, 4 Apr 2013 21:31:03 +0100
Subject: drm/i915: Workaround incoherence between fences and LLC across
multiple CPUs
From: Chris Wilson <[email protected]>
commit 25ff1195f8a0b3724541ae7bbe331b4296de9c06 upstream.
In order to fully serialize access to the fenced region and the update
to the fence register we need to take extreme measures on SNB+, and
manually flush writes to memory prior to writing the fence register in
conjunction with the memory barriers placed around the register write.
Fixes i-g-t/gem_fence_thrash
v2: Bring a bigger gun
v3: Switch the bigger gun for heavier bullets (Arjan van de Ven)
v4: Remove changes for working generations.
v5: Reduce to a per-cpu wbinvd() call prior to updating the fences.
v6: Rewrite comments to ellide forgotten history.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62191
Signed-off-by: Chris Wilson <[email protected]>
Cc: Jon Bloomfield <[email protected]>
Tested-by: Jon Bloomfield <[email protected]> (v2)
Reviewed-by: Jesse Barnes <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
[bwh: Backported to 3.2: insert the cache flush in i915_gem_object_get_fence()]
Signed-off-by: Ben Hutchings <[email protected]>
Cc: Weng Meiling <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/i915/i915_gem.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2468,6 +2468,11 @@ i915_find_fence_reg(struct drm_device *d
return avail;
}
+static void i915_gem_write_fence__ipi(void *data)
+{
+ wbinvd();
+}
+
/**
* i915_gem_object_get_fence - set up a fence reg for an object
* @obj: object to map through a fence reg
@@ -2589,6 +2594,17 @@ update:
switch (INTEL_INFO(dev)->gen) {
case 7:
case 6:
+ /* In order to fully serialize access to the fenced region and
+ * the update to the fence register we need to take extreme
+ * measures on SNB+. In theory, the write to the fence register
+ * flushes all memory transactions before, and coupled with the
+ * mb() placed around the register write we serialise all memory
+ * operations with respect to the changes in the tiler. Yet, on
+ * SNB+ we need to take a step further and emit an explicit
wbinvd()
+ * on each processor in order to manually flush all memory
+ * transactions before updating the fence register.
+ */
+ on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
ret = sandybridge_write_fence_reg(obj, pipelined);
break;
case 5:
Patches currently in stable-queue which might be from [email protected]
are
queue-3.4/drm-i915-only-increment-the-user-pin-count-after-successfully-pinning-the-bo.patch
queue-3.4/drm-i915-add-missing-n-to-uts_release-in-the-error_state.patch
queue-3.4/drm-i915-sdvo-clean-up-connectors-on-intel_sdvo_init-failures.patch
queue-3.4/drm-i915-workaround-incoherence-between-fences-and-llc-across-multiple-cpus.patch
queue-3.4/drm-i915-panel-invert-brightness-via-parameter.patch
queue-3.4/drm-i915-dump-uts_release-into-the-error_state.patch
queue-3.4/drm-i915-close-race-between-processing-unpin-task-and-queueing-the-flip.patch
queue-3.4/drm-i915-panel-invert-brightness-acer-aspire-5734z.patch
queue-3.4/drm-i915-panel-invert-brightness-via-quirk.patch
queue-3.4/drm-pad-drm_mode_get_connector-to-64-bit-boundary.patch
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