From: Jeff Kirsher <[email protected]> Date: Thu, 10 Jul 2014 01:47:15 -0700
> From: Todd Fujinaka <[email protected]> > > On some devices, the internal PLL circuit occasionally provides the > wrong clock frequency after power up. The probability of failure is less > than one failure per 1000 power cycles. When the failure occurs, the > internal clock frequency is around 1/20 of the correct frequency. > > Cc: stable <[email protected]> > Signed-off-by: Todd Fujinaka <[email protected]> > Tested-by: Aaron Brown <[email protected]> > Signed-off-by: Jeff Kirsher <[email protected]> Applied, thanks Jeff. -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
