3.15-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Joel Stanley <[email protected]>

commit f73128f4f680e8be68cda831f2710214559583cb upstream.

These two registers are already saved in the block above. Aside from
being unnecessary, by the time we get down to the second save location
r8 no longer contains MMCR2, so we are clobbering the saved value with
PMC5.

MMCR2 primarily consists of counter freeze bits. So restoring the value
of PMC5 into MMCR2 will most likely have the effect of freezing
counters.

Fixes: 72cde5a88d37 ("KVM: PPC: Book3S HV: Save/restore host PMU registers that 
are new in POWER8")
Signed-off-by: Joel Stanley <[email protected]>
Acked-by: Michael Ellerman <[email protected]>
Acked-by: Paul Mackerras <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
Signed-off-by: Benjamin Herrenschmidt <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>

---
 arch/powerpc/kvm/book3s_hv_interrupts.S |    5 -----
 1 file changed, 5 deletions(-)

--- a/arch/powerpc/kvm/book3s_hv_interrupts.S
+++ b/arch/powerpc/kvm/book3s_hv_interrupts.S
@@ -127,11 +127,6 @@ BEGIN_FTR_SECTION
        stw     r10, HSTATE_PMC + 24(r13)
        stw     r11, HSTATE_PMC + 28(r13)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
-BEGIN_FTR_SECTION
-       mfspr   r9, SPRN_SIER
-       std     r8, HSTATE_MMCR + 40(r13)
-       std     r9, HSTATE_MMCR + 48(r13)
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 31:
 
        /*


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