Hi Jens, For a test, I'd try:
a. there could be a phase shift on the data bus signals due to different fpga routing. http://192.168.0.9/parsedit.php?embed=0.15&title=Phase+Adjustment&DAEMON_EN&SENSOR_PHASE&MULTI_PHASE1&MULTI_PHASE2&MULTI_PHASE3&QUALITY&TESTSENSOR&FPGATEST&FRAME_SIZE a1. Set TESTSENSOR to 0x1 - vertical color bars: http://wiki.elphel.com/index.php?title=File:Reference_img.jpeg a2. Try to change MULTI_PHASE1 & SENSOR_PHASE b. 'connect' > spx_vact1 > spx_hact1 > spxd1 - these are the incoming signals from the sensor in J2. They are sync to sclk0 and connecting them to the output signals (sync to sclk0 as well) that go to the system board: > ivact > ihact > pxdr c. Try to output a counter from your module. Regards, Oleg _______________________________________________ Support-list mailing list [email protected] http://support.elphel.com/mailman/listinfo/support-list_support.elphel.com
