Author: sam
Date: Wed May 6 23:09:26 2009
New Revision: 191864
URL: http://svn.freebsd.org/changeset/base/191864
Log:
add support for the Beacon Not Ready (BNR) interrupt
(available on 5211 and later)
Modified:
head/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c
head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c
head/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c Wed May 6 22:40:01
2009 (r191863)
+++ head/sys/dev/ath/ath_hal/ar5211/ar5211_interrupts.c Wed May 6 23:09:26
2009 (r191864)
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5211_interrupts.c,v 1.6 2008/11/27 22:29:52 sam Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"
@@ -64,6 +64,8 @@ ar5211GetPendingInterrupts(struct ath_ha
*masked |= HAL_INT_RX;
if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL))
*masked |= HAL_INT_TX;
+ if (isr & AR_ISR_BNR)
+ *masked |= HAL_INT_BNR;
/*
* Receive overrun is usually non-fatal on Oahu/Spirit.
* BUT on some parts rx could fail and the chip must be reset.
@@ -137,6 +139,8 @@ ar5211SetInterrupts(struct ath_hal *ah,
}
if (ints & HAL_INT_RX)
mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC;
+ if (ints & AR_ISR_BNR)
+ mask |= HAL_INT_BNR;
if (ints & HAL_INT_FATAL) {
/*
* NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c Wed May 6 22:40:01
2009 (r191863)
+++ head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c Wed May 6 23:09:26
2009 (r191864)
@@ -14,7 +14,7 @@
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
- * $Id: ar5212_interrupts.c,v 1.6 2008/11/27 22:30:00 sam Exp $
+ * $FreeBSD$
*/
#include "opt_ah.h"
@@ -92,6 +92,8 @@ ar5212GetPendingInterrupts(struct ath_ha
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
}
+ if (isr & AR_ISR_BNR)
+ *masked |= HAL_INT_BNR;
/*
* Receive overrun is usually non-fatal on Oahu/Spirit.
@@ -173,6 +175,8 @@ ar5212SetInterrupts(struct ath_hal *ah,
if (ints & HAL_INT_CABEND)
mask2 |= (AR_IMR_S2_CABEND );
}
+ if (ints & HAL_INT_BNR)
+ mask |= AR_IMR_BNR;
if (ints & HAL_INT_FATAL) {
/*
* NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2
Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c Wed May 6 22:40:01
2009 (r191863)
+++ head/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c Wed May 6 23:09:26
2009 (r191864)
@@ -119,6 +119,8 @@ ar5416GetPendingInterrupts(struct ath_ha
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR);
ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL);
}
+ if (isr & AR_ISR_BNR)
+ *masked |= HAL_INT_BNR;
/* Interrupt Mitigation on AR5416 */
#ifdef AR5416_INT_MITIGATION
@@ -227,6 +229,8 @@ ar5416SetInterrupts(struct ath_hal *ah,
if (ints & HAL_INT_TSFOOR)
mask2 |= AR_IMR_S2_TSFOOR;
}
+ if (ints & HAL_INT_BNR)
+ mask |= AR_IMR_BNR;
/* Write the new IMR and store off our SW copy. */
HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask);
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