Author: neel
Date: Fri May  1 16:00:29 2015
New Revision: 282301
URL: https://svnweb.freebsd.org/changeset/base/282301

Log:
  r281630 relaxed the limits on the vectors that can be asserted in the IRRs.
  
  Do the same when transitioning a vector from the IRR to the ISR and also
  when extinguishing it from the ISR in response to an EOI.
  
  Reported by:  Leon Dang ([email protected])
  MFC after:    2 weeks

Modified:
  head/sys/amd64/vmm/io/vlapic.c

Modified: head/sys/amd64/vmm/io/vlapic.c
==============================================================================
--- head/sys/amd64/vmm/io/vlapic.c      Fri May  1 12:49:03 2015        
(r282300)
+++ head/sys/amd64/vmm/io/vlapic.c      Fri May  1 16:00:29 2015        
(r282301)
@@ -547,6 +547,8 @@ vlapic_update_ppr(struct vlapic *vlapic)
        VLAPIC_CTR1(vlapic, "vlapic_update_ppr 0x%02x", ppr);
 }
 
+static VMM_STAT(VLAPIC_GRATUITOUS_EOI, "EOI without any in-service interrupt");
+
 static void
 vlapic_process_eoi(struct vlapic *vlapic)
 {
@@ -557,11 +559,7 @@ vlapic_process_eoi(struct vlapic *vlapic
        isrptr = &lapic->isr0;
        tmrptr = &lapic->tmr0;
 
-       /*
-        * The x86 architecture reserves the the first 32 vectors for use
-        * by the processor.
-        */
-       for (i = 7; i > 0; i--) {
+       for (i = 7; i >= 0; i--) {
                idx = i * 4;
                bitpos = fls(isrptr[idx]);
                if (bitpos-- != 0) {
@@ -570,17 +568,21 @@ vlapic_process_eoi(struct vlapic *vlapic
                                      vlapic->isrvec_stk_top);
                        }
                        isrptr[idx] &= ~(1 << bitpos);
+                       vector = i * 32 + bitpos;
+                       VCPU_CTR1(vlapic->vm, vlapic->vcpuid, "EOI vector %d",
+                           vector);
                        VLAPIC_CTR_ISR(vlapic, "vlapic_process_eoi");
                        vlapic->isrvec_stk_top--;
                        vlapic_update_ppr(vlapic);
                        if ((tmrptr[idx] & (1 << bitpos)) != 0) {
-                               vector = i * 32 + bitpos;
                                vioapic_process_eoi(vlapic->vm, vlapic->vcpuid,
                                    vector);
                        }
                        return;
                }
        }
+       VCPU_CTR0(vlapic->vm, vlapic->vcpuid, "Gratuitous EOI");
+       vmm_stat_incr(vlapic->vm, vlapic->vcpuid, VLAPIC_GRATUITOUS_EOI, 1);
 }
 
 static __inline int
@@ -1092,11 +1094,7 @@ vlapic_pending_intr(struct vlapic *vlapi
 
        irrptr = &lapic->irr0;
 
-       /*
-        * The x86 architecture reserves the the first 32 vectors for use
-        * by the processor.
-        */
-       for (i = 7; i > 0; i--) {
+       for (i = 7; i >= 0; i--) {
                idx = i * 4;
                val = atomic_load_acq_int(&irrptr[idx]);
                bitpos = fls(val);
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