Author: yongari
Date: Thu Jun 18 04:58:04 2009
New Revision: 194417
URL: http://svn.freebsd.org/changeset/base/194417

Log:
  MFC r193291:
    Program LED registers for 88E1116/88E1149 PHYs. These PHYs are
    found on Marvell Yukon Ultra, Marvell Yukon Extreme controllers.
    While I'm here explicitly issue 'powerup' command for 88E1149 PHY.
  
    Tested by:  jhb, Warren Block ( wblock <> wonkity dot com )

Modified:
  stable/7/sys/   (props changed)
  stable/7/sys/contrib/pf/   (props changed)
  stable/7/sys/dev/mii/e1000phy.c
  stable/7/sys/dev/mii/e1000phyreg.h

Modified: stable/7/sys/dev/mii/e1000phy.c
==============================================================================
--- stable/7/sys/dev/mii/e1000phy.c     Thu Jun 18 04:55:04 2009        
(r194416)
+++ stable/7/sys/dev/mii/e1000phy.c     Thu Jun 18 04:58:04 2009        
(r194417)
@@ -237,7 +237,8 @@ e1000phy_reset(struct mii_softc *sc)
                }
                PHY_WRITE(sc, E1000_SCR, reg);
 
-               if (esc->mii_model == MII_MODEL_MARVELL_E1116) {
+               if (esc->mii_model == MII_MODEL_MARVELL_E1116 ||
+                   esc->mii_model == MII_MODEL_MARVELL_E1149) {
                        page = PHY_READ(sc, E1000_EADR);
                        /* Select page 2, MAC specific control register. */
                        PHY_WRITE(sc, E1000_EADR, 2);
@@ -251,9 +252,22 @@ e1000phy_reset(struct mii_softc *sc)
        switch (MII_MODEL(esc->mii_model)) {
        case MII_MODEL_MARVELL_E3082:
        case MII_MODEL_MARVELL_E1112:
-       case MII_MODEL_MARVELL_E1116:
        case MII_MODEL_MARVELL_E1118:
+               break;
+       case MII_MODEL_MARVELL_E1116:
        case MII_MODEL_MARVELL_E1149:
+               page = PHY_READ(sc, E1000_EADR);
+               /* Select page 3, LED control register. */
+               PHY_WRITE(sc, E1000_EADR, 3);
+               PHY_WRITE(sc, E1000_SCR,
+                   E1000_SCR_LED_LOS(1) |      /* Link/Act */
+                   E1000_SCR_LED_INIT(8) |     /* 10Mbps */
+                   E1000_SCR_LED_STAT1(7) |    /* 100Mbps */
+                   E1000_SCR_LED_STAT0(7));    /* 1000Mbps */
+               /* Set blink rate. */
+               PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
+                   E1000_BLINK_RATE(E1000_BLINK_84MS));
+               PHY_WRITE(sc, E1000_EADR, page);
                break;
        case MII_MODEL_MARVELL_E3016:
                /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */

Modified: stable/7/sys/dev/mii/e1000phyreg.h
==============================================================================
--- stable/7/sys/dev/mii/e1000phyreg.h  Thu Jun 18 04:55:04 2009        
(r194416)
+++ stable/7/sys/dev/mii/e1000phyreg.h  Thu Jun 18 04:58:04 2009        
(r194417)
@@ -256,9 +256,19 @@
 
 /* 88E1116 page 0 */
 #define        E1000_SCR_POWER_DOWN            0x0004
-/* 88E1116 page 2 */
+/* 88E1116, 88E1149 page 2 */
 #define        E1000_SCR_RGMII_POWER_UP        0x0008
 
+/* 88E1116, 88E1149 page 3 */
+#define E1000_SCR_LED_STAT0_MASK       0x000F
+#define E1000_SCR_LED_STAT1_MASK       0x00F0
+#define E1000_SCR_LED_INIT_MASK                0x0F00
+#define E1000_SCR_LED_LOS_MASK         0xF000
+#define E1000_SCR_LED_STAT0(x)         ((x) & E1000_SCR_LED_STAT0_MASK)
+#define E1000_SCR_LED_STAT1(x)         ((x) & E1000_SCR_LED_STAT1_MASK)
+#define E1000_SCR_LED_INIT(x)          ((x) & E1000_SCR_LED_INIT_MASK)
+#define E1000_SCR_LED_LOS(x)           ((x) & E1000_SCR_LED_LOS_MASK)
+
 #define E1000_SSR                      0x11    /* special status register */
 #define E1000_SSR_JABBER               0x0001
 #define E1000_SSR_REV_POLARITY         0x0002
@@ -286,6 +296,26 @@
 #define E1000_IER_SPEED_CHANGED                0x4000
 #define E1000_IER_AUTO_NEG_ERR         0x8000
 
+/* 88E1116, 88E1149 page 3, LED timer control. */
+#define        E1000_PULSE_MASK        0x7000
+#define        E1000_PULSE_NO_STR      0       /* no pulse stretching */
+#define        E1000_PULSE_21MS        1       /* 21 ms to 42 ms */
+#define        E1000_PULSE_42MS        2       /* 42 ms to 84 ms */
+#define        E1000_PULSE_84MS        3       /* 84 ms to 170 ms */
+#define        E1000_PULSE_170MS       4       /* 170 ms to 340 ms */
+#define        E1000_PULSE_340MS       5       /* 340 ms to 670 ms */
+#define        E1000_PULSE_670MS       6       /* 670 ms to 1300 ms */
+#define        E1000_PULSE_1300MS      7       /* 1300 ms to 2700 ms */
+#define        E1000_PULSE_DUR(x)      ((x) &  E1000_PULSE_MASK) 
+
+#define        E1000_BLINK_MASK        0x0700
+#define        E1000_BLINK_42MS        0       /* 42 ms */
+#define        E1000_BLINK_84MS        1       /* 84 ms */
+#define        E1000_BLINK_170MS       2       /* 170 ms */
+#define        E1000_BLINK_340MS       3       /* 340 ms */
+#define        E1000_BLINK_670MS       4       /* 670 ms */
+#define        E1000_BLINK_RATE(x)     ((x) &  E1000_BLINK_MASK) 
+
 #define E1000_ISR                      0x13    /* interrupt status reg */
 #define E1000_ISR_JABBER               0x0001
 #define E1000_ISR_POLARITY_CHANGE      0x0002
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