Author: avg
Date: Fri Apr 22 13:44:12 2016
New Revision: 298473
URL: https://svnweb.freebsd.org/changeset/base/298473
Log:
lahf/sahf are supported on some amd64 processors
While the instructions were not included into the original instruction
set, their support can be indicated by a special feature bit.
For example:
CPU: AMD Phenom(tm) II X4 955 Processor (3214.71-MHz K8-class CPU)
...
AMD Features2=0x37ff<LAHF, ...>
Clang 3.8 uses lahf/sahf as a faster alternative to pushf/popf where
possible.
MFC after: 2 weeks
Modified:
head/sys/cddl/dev/dtrace/x86/dis_tables.c
Modified: head/sys/cddl/dev/dtrace/x86/dis_tables.c
==============================================================================
--- head/sys/cddl/dev/dtrace/x86/dis_tables.c Fri Apr 22 13:00:27 2016
(r298472)
+++ head/sys/cddl/dev/dtrace/x86/dis_tables.c Fri Apr 22 13:44:12 2016
(r298473)
@@ -1931,7 +1931,7 @@ const instable_t dis_distable[16][16] =
/* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA),
TS("xchg",RA),
/* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA),
TS("xchg",RA),
/* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD),
TNSx("lcall",SO), TNS("fwait",NORM),
-/* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4),
TNSx("sahf",NORM), TNSx("lahf",NORM),
+/* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4),
TNS("sahf",NORM), TNS("lahf",NORM),
}, {
/* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO),
TS("mov",AO),
/* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD),
TNSZ("cmpsb",SD,1), TS("cmps",SD),
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