Author: adrian
Date: Fri May 13 18:41:36 2016
New Revision: 299689
URL: https://svnweb.freebsd.org/changeset/base/299689
Log:
[bwn] add N-PHY related register defintions.
* Add the siba bus phy/mac/bandwidth clock definitions (TGSLOW*)
* Add the PHY-N register gateway (BWN_PHY_N())
* Add the PHY-N TX phystat1 register - we need to actually fill out
more of the PHY encoding information when we assemble a frame.
* Various ancillary stuff
Nothing uses this yet, but I do have CCK/OFDM somewhat working
in 2GHz mode on a PHY-N device.
Obtained from: b43 (definitions)
Modified:
head/sys/dev/bwn/if_bwnreg.h
Modified: head/sys/dev/bwn/if_bwnreg.h
==============================================================================
--- head/sys/dev/bwn/if_bwnreg.h Fri May 13 18:20:54 2016
(r299688)
+++ head/sys/dev/bwn/if_bwnreg.h Fri May 13 18:41:36 2016
(r299689)
@@ -56,9 +56,17 @@
#define BWN_BFH_LDO_PAREF 0x0004
#define BWN_BFH_FEM_BT 0x0040
-#define BWN_TGSLOW_SUPPORT_G 0x20000000
-#define BWN_TGSLOW_PHYRESET 0x00080000
#define BWN_TGSLOW_PHYCLOCK_ENABLE 0x00040000
+#define BWN_TGSLOW_PHYRESET 0x00080000
+#define BWN_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY
Clock Control Enable (rev >= 5) */
+#define BWN_TMSLOW_PLLREFSEL 0x00200000 /* PLL
Frequency Reference Select (rev >= 5) */
+/* PHY_BANDWIDTH: N-PHY only */
+#define BWN_TGSLOW_PHY_BANDWIDTH 0x00C00000
+#define BWN_TGSLOW_PHY_BANDWIDTH_10MHZ 0x00000000
+#define BWN_TGSLOW_PHY_BANDWIDTH_20MHZ 0x00400000
+#define BWN_TGSLOW_PHY_BANDWIDTH_40MHZ 0x00800000
+#define BWN_TGSLOW_SUPPORT_G 0x20000000
+
#define BWN_TGSHIGH_HAVE_2GHZ 0x00010000
#define BWN_TGSHIGH_HAVE_5GHZ 0x00020000
@@ -85,6 +93,7 @@
#define BWN_DMA4_REASON 0x40
#define BWN_DMA4_INTR_MASK 0x44
#define BWN_DMA5_INTR_MASK 0x4c
+
#define BWN_MACCTL 0x120
#define BWN_MACCTL_ON 0x00000001
#define BWN_MACCTL_MCODE_RUN 0x00000002
@@ -98,12 +107,18 @@
#define BWN_MACCTL_RADIO_LOCK 0x00080000
#define BWN_MACCTL_BEACON_PROMISC 0x00100000
#define BWN_MACCTL_PASS_BADPLCP 0x00200000
+#define BWN_MACCTL_PHY_LOCK 0x00200000 /* PHY-N? */
#define BWN_MACCTL_PASS_CTL 0x00400000
#define BWN_MACCTL_PASS_BADFCS 0x00800000
#define BWN_MACCTL_PROMISC 0x01000000
#define BWN_MACCTL_HWPS 0x02000000
#define BWN_MACCTL_AWAKE 0x04000000
+#define BWN_MACCTL_CLOSEDNET 0x08000000
+#define BWN_MACCTL_TBTT_HOLD 0x10000000
+#define BWN_MACCTL_DISC_TXSTAT 0x20000000
+#define BWN_MACCTL_DISC_PMQ 0x40000000
#define BWN_MACCTL_GMODE 0x80000000
+
#define BWN_MACCMD 0x124 /* MAC command */
#define BWN_MACCMD_BEACON0_VALID 0x00000001
#define BWN_MACCMD_BEACON1_VALID 0x00000002
@@ -175,6 +190,13 @@
#define BWN_MACFILTER_CONTROL 0x420
#define BWN_MACFILTER_DATA 0x422
#define BWN_RCMTA_COUNT 0x43c
+
+#define BWN_PSM_PHY_HDR 0x492
+/* BWN_PSM_PHY_HDR bits */
+#define BWN_PSM_HDR_MAC_PHY_RESET 0x00000001
+#define BWN_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002
+#define BWN_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004
+
#define BWN_RF_HWENABLED_LO 0x49a
#define BWN_RF_HWENABLED_LO_MASK (1 << 4)
#define BWN_GPIO_CONTROL 0x49c
@@ -182,6 +204,8 @@
#define BWN_TSF_CFP_START_LOW 0x604
#define BWN_TSF_CFP_START_HIGH 0x606
#define BWN_TSF_CFP_PRETBTT 0x612
+#define BWN_TSF_CLK_FRAC_LOW 0x62e
+#define BWN_TSF_CLK_FRAC_HIGH 0x630
#define BWN_RNG 0x65a
#define BWN_IFSCTL 0x688 /* Interframe space
control */
#define BWN_IFSCTL_USE_EDCF 0x0004
@@ -226,6 +250,15 @@
#define BWN_SHARED_KEYIDX_BLOCK 0x05d4
#define BWN_SHARED_PSM 0x05f4
+/* SHM_SHARED tx iq workarounds */
+#define BWN_SHM_SH_NPHY_TXIQW0 0x0700
+#define BWN_SHM_SH_NPHY_TXIQW1 0x0702
+#define BWN_SHM_SH_NPHY_TXIQW2 0x0704
+#define BWN_SHM_SH_NPHY_TXIQW3 0x0706
+/* SHM_SHARED tx pwr ctrl */
+#define BWN_SHM_SH_NPHY_TXPWR_INDX0 0x0708
+#define BWN_SHM_SH_NPHY_TXPWR_INDX1 0x070E
+
/* SHM_SCRATCH offsets */
#define BWN_SCRATCH 0x2
#define BWN_SCRATCH_CONT_MIN 0x0003
@@ -272,6 +305,13 @@
#define BWN_HF_HW_POWERCTL 0x000000800000ull
#define BWN_HF_BT_COEXISTALT 0x000001000000ull
#define BWN_HF_SKIP_CFP_UPDATE 0x000004000000ull
+#define BWN_HF_N40W 0x000008000000ULL /* N PHY 40
MHz workaround (rev >= 13 only) */
+#define BWN_HF_ANTSEL 0x000020000000ULL /* Antenna
selection (for testing antenna div.) */
+#define BWN_HF_BT3COEXT 0x000020000000ULL /* Bluetooth
3-wire coexistence (rev >= 13 only) */
+#define BWN_HF_BTCANT 0x000040000000ULL /* Bluetooth
coexistence (antenna mode) (rev >= 13 only) */
+#define BWN_HF_ANTSELEN 0x000100000000ULL /* Antenna
selection enabled (rev >= 13 only) */
+#define BWN_HF_ANTSELMODE 0x000200000000ULL /* Antenna
selection mode (rev >= 13 only) */
+#define BWN_HF_MLADVW 0x001000000000ULL /* N PHY ML
ADV workaround (rev >= 13 only) */
#define BWN_HF_PR45960W 0x080000000000ULL
#define BWN_TX_PHY_ENC_CCK 0x0000
@@ -380,9 +420,12 @@
#define BWN_DMA0_RX_BUFFERSIZE IEEE80211_MAX_LEN
#define BWN_PHYROUTE_BASE 0x0000
+#define BWN_PHYROUTE_MASK 0x0c00
#define BWN_PHYROUTE_OFDM_GPHY 0x0400
#define BWN_PHYROUTE_EXT_GPHY 0x0800
+#define BWN_PHYROUTE_N_BMODE 0x0C00
#define BWN_PHY_CCK(reg) ((reg) | BWN_PHYROUTE_BASE)
+#define BWN_PHY_N(reg) ((reg) | BWN_PHYROUTE_BASE) /*
PHY-N */
#define BWN_PHY_N_BMODE(reg) ((reg) | BWN_PHYROUTE_N_BMODE)
#define BWN_PHY_OFDM(reg) ((reg) | BWN_PHYROUTE_OFDM_GPHY)
#define BWN_PHY_EXTG(reg) ((reg) | BWN_PHYROUTE_EXT_GPHY)
@@ -1001,4 +1044,32 @@
#define BWN_B2063_PA_CTL11 BWN_LP_RADIO(0x115)
#define BWN_B2063_VREG_CTL1 BWN_LP_RADIO(0x11D)
+/* N-PHY, etc TX configuration */
+
+#define BWN_TXH_PHY1_BW 0x0007 /* Bandwidth */
+#define BWN_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
+#define BWN_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
+#define BWN_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
+#define BWN_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
+#define BWN_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
+#define BWN_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */
+#define BWN_TXH_PHY1_MODE 0x0038 /* Mode */
+#define BWN_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
+#define BWN_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
+#define BWN_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
+#define BWN_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
+#define BWN_TXH_PHY1_CRATE 0x0700 /* Coding rate */
+#define BWN_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
+#define BWN_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
+#define BWN_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
+#define BWN_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
+#define BWN_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
+#define BWN_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
+#define BWN_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
+#define BWN_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
+#define BWN_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
+#define BWN_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
+#define BWN_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
+#define BWN_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
+
#endif /* !_IF_BWNREG_H */
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