Author: mmel Date: Sat Oct 15 07:38:27 2016 New Revision: 307342 URL: https://svnweb.freebsd.org/changeset/base/307342
Log: MFC r306755: ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores. Not a functional change. Modified: stable/11/sys/arm/arm/cpuinfo.c stable/11/sys/arm/include/cpuinfo.h Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/arm/arm/cpuinfo.c ============================================================================== --- stable/11/sys/arm/arm/cpuinfo.c Sat Oct 15 07:30:13 2016 (r307341) +++ stable/11/sys/arm/arm/cpuinfo.c Sat Oct 15 07:38:27 2016 (r307342) @@ -163,7 +163,11 @@ cpuinfo_get_actlr_modifier(uint32_t *act if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) { switch (cpuinfo.part_number) { - + case CPU_ARCH_CORTEX_A72: + case CPU_ARCH_CORTEX_A57: + case CPU_ARCH_CORTEX_A53: + /* Nothing to do for AArch32 */ + break; case CPU_ARCH_CORTEX_A17: case CPU_ARCH_CORTEX_A12: /* A12 is merged to A17 */ /* Modified: stable/11/sys/arm/include/cpuinfo.h ============================================================================== --- stable/11/sys/arm/include/cpuinfo.h Sat Oct 15 07:30:13 2016 (r307341) +++ stable/11/sys/arm/include/cpuinfo.h Sat Oct 15 07:38:27 2016 (r307342) @@ -45,10 +45,18 @@ #define CPU_ARCH_CORTEX_A12 0xC0D #define CPU_ARCH_CORTEX_A15 0xC0F #define CPU_ARCH_CORTEX_A17 0xC11 +#define CPU_ARCH_CORTEX_A53 0xD03 +#define CPU_ARCH_CORTEX_A57 0xD07 +#define CPU_ARCH_CORTEX_A72 0xD08 + /* QCOM */ #define CPU_ARCH_KRAIT_300 0x06F +/* MRVL */ +#define CPU_ARCH_SHEEVA_851 0x581 /* PJ4/PJ4B */ +#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */ + struct cpuinfo { /* raw id registers */ uint32_t midr; _______________________________________________ svn-src-all@freebsd.org mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "svn-src-all-unsubscr...@freebsd.org"