Author: jhibbits
Date: Thu Dec 22 20:16:10 2016
New Revision: 310427
URL: https://svnweb.freebsd.org/changeset/base/310427

Log:
  Partial MFC r303693:
  
    Merge MPC85XX and QorIQ config options
  
  Only a partial MFC, keeping files.powerpc and options.powerpc intact, to
  retain compatibility with any kernel configs that may use the QORIQ_DPAA 
option.

Modified:
  stable/11/sys/powerpc/conf/MPC85XX
  stable/11/sys/powerpc/conf/dpaa/DPAA
  stable/11/sys/powerpc/mpc85xx/mpc85xx.c
  stable/11/sys/powerpc/mpc85xx/mpc85xx.h
  stable/11/sys/powerpc/mpc85xx/pci_mpc85xx.c
  stable/11/sys/powerpc/mpc85xx/platform_mpc85xx.c
Directory Properties:
  stable/11/   (props changed)

Modified: stable/11/sys/powerpc/conf/MPC85XX
==============================================================================
--- stable/11/sys/powerpc/conf/MPC85XX  Thu Dec 22 18:30:29 2016        
(r310426)
+++ stable/11/sys/powerpc/conf/MPC85XX  Thu Dec 22 20:16:10 2016        
(r310427)
@@ -10,7 +10,9 @@ ident         MPC85XX
 
 machine                powerpc powerpc
 
+include        "dpaa/config.dpaa"
 makeoptions    DEBUG="-Wa,-me500 -g"
+makeoptions    WERROR="-Werror -Wno-format -Wno-redundant-decls"
 makeoptions    NO_MODULES=yes
 
 options        FPU_EMU
@@ -21,7 +23,6 @@ options       BREAK_TO_DEBUGGER
 options        BOOTP
 options        BOOTP_NFSROOT
 #options       BOOTP_NFSV3
-options        BOOTP_WIRED_TO=tsec0
 options        CD9660
 options        COMPAT_43
 options        DDB
@@ -29,7 +30,6 @@ options       DDB
 options        DEVICE_POLLING
 #options       DIAGNOSTIC
 options        FDT
-makeoptions    FDT_DTS_FILE=mpc8572ds.dts
 #makeoptions   FDT_DTS_FILE=mpc8555cds.dts
 options        FFS
 options        GDB
@@ -69,6 +69,7 @@ device                em
 device         alc
 device         ether
 device         fxp
+device         gpio
 device         iic
 device         iicbus
 #device                isa

Modified: stable/11/sys/powerpc/conf/dpaa/DPAA
==============================================================================
--- stable/11/sys/powerpc/conf/dpaa/DPAA        Thu Dec 22 18:30:29 2016        
(r310426)
+++ stable/11/sys/powerpc/conf/dpaa/DPAA        Thu Dec 22 20:16:10 2016        
(r310427)
@@ -16,7 +16,7 @@ makeoptions   WERROR="-Werror -Wno-format 
 makeoptions    NO_MODULES=yes
 
 # Platform support
-options                QORIQ_DPAA              #Freescale SoC family
+options                MPC85XX                 #Freescale SoC family
 
 options                SMP                     #Symmetric Multi Processing
 

Modified: stable/11/sys/powerpc/mpc85xx/mpc85xx.c
==============================================================================
--- stable/11/sys/powerpc/mpc85xx/mpc85xx.c     Thu Dec 22 18:30:29 2016        
(r310426)
+++ stable/11/sys/powerpc/mpc85xx/mpc85xx.c     Thu Dec 22 20:16:10 2016        
(r310427)
@@ -108,13 +108,17 @@ law_getmax(void)
 static inline void
 law_write(uint32_t n, uint64_t bar, uint32_t sr)
 {
-#if defined(QORIQ_DPAA)
-       ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
-       ccsr_write4(OCP85XX_LAWBARL(n), bar);
-#else
-       ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
-#endif
-       ccsr_write4(OCP85XX_LAWSR(n), sr);
+
+       if (mpc85xx_is_qoriq()) {
+               ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32);
+               ccsr_write4(OCP85XX_LAWBARL(n), bar);
+               ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr);
+               ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
+       } else {
+               ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12);
+               ccsr_write4(OCP85XX_LAWSR_85XX(n), sr);
+               ccsr_read4(OCP85XX_LAWSR_85XX(n));
+       }
 
        /*
         * The last write to LAWAR should be followed by a read
@@ -123,20 +127,21 @@ law_write(uint32_t n, uint64_t bar, uint
         * instruction.
         */
 
-       ccsr_read4(OCP85XX_LAWSR(n));
        isync();
 }
 
 static inline void
 law_read(uint32_t n, uint64_t *bar, uint32_t *sr)
 {
-#if defined(QORIQ_DPAA)
-       *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
-           ccsr_read4(OCP85XX_LAWBARL(n));
-#else
-       *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
-#endif
-       *sr = ccsr_read4(OCP85XX_LAWSR(n));
+
+       if (mpc85xx_is_qoriq()) {
+               *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 |
+                   ccsr_read4(OCP85XX_LAWBARL(n));
+               *sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n));
+       } else {
+               *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12;
+               *sr = ccsr_read4(OCP85XX_LAWSR_85XX(n));
+       }
 }
 
 static int
@@ -306,6 +311,18 @@ mpc85xx_enable_l3_cache(void)
        }
 }
 
+int
+mpc85xx_is_qoriq(void)
+{
+       uint16_t pvr = mfpvr() >> 16;
+
+       /* QorIQ register set is only in e500mc and derivative core based SoCs. 
*/
+       if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500)
+               return (1);
+
+       return (0);
+}
+
 static void
 mpc85xx_dataloss_erratum_spr976(void)
 {
@@ -352,9 +369,7 @@ moveon:
        if (err != 0)
                return (err);
 
-#ifdef QORIQ_DPAA
        law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000);
-#endif
        return pmap_early_io_map(b, 0x400000);
 }
 

Modified: stable/11/sys/powerpc/mpc85xx/mpc85xx.h
==============================================================================
--- stable/11/sys/powerpc/mpc85xx/mpc85xx.h     Thu Dec 22 18:30:29 2016        
(r310426)
+++ stable/11/sys/powerpc/mpc85xx/mpc85xx.h     Thu Dec 22 20:16:10 2016        
(r310427)
@@ -67,36 +67,44 @@ extern vm_offset_t          ccsrbar_va;
 /*
  * Local access registers
  */
-#if defined(QORIQ_DPAA)
 /* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */
 #define        OCP85XX_LAWBARH(n)      (CCSRBAR_VA + 0xc00 + 0x10 * (n))
 #define        OCP85XX_LAWBARL(n)      (CCSRBAR_VA + 0xc04 + 0x10 * (n))
-#define        OCP85XX_LAWSR(n)        (CCSRBAR_VA + 0xc08 + 0x10 * (n))
-#else
+#define        OCP85XX_LAWSR_QORIQ(n)  (CCSRBAR_VA + 0xc08 + 0x10 * (n))
 #define        OCP85XX_LAWBAR(n)       (CCSRBAR_VA + 0xc08 + 0x10 * (n))
-#define        OCP85XX_LAWSR(n)        (CCSRBAR_VA + 0xc10 + 0x10 * (n))
-#endif
+#define        OCP85XX_LAWSR_85XX(n)   (CCSRBAR_VA + 0xc10 + 0x10 * (n))
+#define        OCP85XX_LAWSR(n)        (mpc85xx_is_qoriq() ? 
OCP85XX_LAWSR_QORIQ(n) : \
+                                OCP85XX_LAWSR_85XX(n))
 
 /* Attribute register */
 #define        OCP85XX_ENA_MASK        0x80000000
 #define        OCP85XX_DIS_MASK        0x7fffffff
 
-#if defined(QORIQ_DPAA)
-#define        OCP85XX_TGTIF_LBC       0x1f
-#define        OCP85XX_TGTIF_RAM_INTL  0x14
-#define        OCP85XX_TGTIF_RAM1      0x10
-#define        OCP85XX_TGTIF_RAM2      0x11
-#define        OCP85XX_TGTIF_BMAN      0x18
-#define        OCP85XX_TGTIF_DCSR      0x1D
-#define        OCP85XX_TGTIF_QMAN      0x3C
-#define        OCP85XX_TRGT_SHIFT      20
-#else
-#define        OCP85XX_TGTIF_LBC       0x04
-#define        OCP85XX_TGTIF_RAM_INTL  0x0b
-#define        OCP85XX_TGTIF_RIO       0x0c
-#define        OCP85XX_TGTIF_RAM1      0x0f
-#define        OCP85XX_TGTIF_RAM2      0x16
-#endif
+#define        OCP85XX_TGTIF_LBC_QORIQ 0x1f
+#define        OCP85XX_TGTIF_RAM_INTL_QORIQ    0x14
+#define        OCP85XX_TGTIF_RAM1_QORIQ        0x10
+#define        OCP85XX_TGTIF_RAM2_QORIQ        0x11
+#define        OCP85XX_TGTIF_BMAN              0x18
+#define        OCP85XX_TGTIF_DCSR              0x1D
+#define        OCP85XX_TGTIF_QMAN              0x3C
+#define        OCP85XX_TRGT_SHIFT_QORIQ        20
+
+#define        OCP85XX_TGTIF_LBC_85XX  0x04
+#define        OCP85XX_TGTIF_RAM_INTL_85XX     0x0b
+#define        OCP85XX_TGTIF_RIO_85XX  0x0c
+#define        OCP85XX_TGTIF_RAM1_85XX 0x0f
+#define        OCP85XX_TGTIF_RAM2_85XX 0x16
+
+#define        OCP85XX_TGTIF_LBC       \
+    (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX)
+#define        OCP85XX_TGTIF_RAM_INTL  \
+     (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : 
OCP85XX_TGTIF_RAM_INTL_85XX)
+#define        OCP85XX_TGTIF_RIO       \
+      (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX)
+#define        OCP85XX_TGTIF_RAM1      \
+       (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : 
OCP85XX_TGTIF_RAM1_85XX)
+#define        OCP85XX_TGTIF_RAM2      \
+       (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : 
OCP85XX_TGTIF_RAM2_85XX)
 
 /*
  * L2 cache registers
@@ -153,5 +161,6 @@ int mpc85xx_attach(platform_t);
 void mpc85xx_enable_l3_cache(void);
 void mpc85xx_fix_errata(vm_offset_t);
 void dataloss_erratum_access(vm_offset_t, uint32_t);
+int mpc85xx_is_qoriq(void);
 
 #endif /* _MPC85XX_H_ */

Modified: stable/11/sys/powerpc/mpc85xx/pci_mpc85xx.c
==============================================================================
--- stable/11/sys/powerpc/mpc85xx/pci_mpc85xx.c Thu Dec 22 18:30:29 2016        
(r310426)
+++ stable/11/sys/powerpc/mpc85xx/pci_mpc85xx.c Thu Dec 22 20:16:10 2016        
(r310427)
@@ -655,7 +655,8 @@ fsl_pcib_inbound(struct fsl_pcib_softc *
 
        switch (tgt) {
        /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
-       case OCP85XX_TGTIF_RAM1:
+       case OCP85XX_TGTIF_RAM1_85XX:
+       case OCP85XX_TGTIF_RAM1_QORIQ:
                attr = 0xa0f55000 | (ffsl(size) - 2);
                break;
        default:

Modified: stable/11/sys/powerpc/mpc85xx/platform_mpc85xx.c
==============================================================================
--- stable/11/sys/powerpc/mpc85xx/platform_mpc85xx.c    Thu Dec 22 18:30:29 
2016        (r310426)
+++ stable/11/sys/powerpc/mpc85xx/platform_mpc85xx.c    Thu Dec 22 20:16:10 
2016        (r310427)
@@ -258,16 +258,17 @@ mpc85xx_timebase_freq(platform_t plat, s
            sizeof(freq)) <= 0)
                goto out;
 
+       if (freq == 0)
+               goto out;
+
        /*
         * Time Base and Decrementer are updated every 8 CCB bus clocks.
         * HID0[SEL_TBCLK] = 0
         */
-       if (freq != 0)
-#ifdef QORIQ_DPAA
+       if (mpc85xx_is_qoriq())
                ticks = freq / 32;
-#else
+       else
                ticks = freq / 8;
-#endif
 
 out:
        if (ticks <= 0)
@@ -324,24 +325,24 @@ mpc85xx_smp_start_cpu(platform_t plat, s
        int timeout;
        uintptr_t brr;
        int cpuid;
-
-#ifdef QORIQ_DPAA
        uint32_t tgt;
 
-       reg = ccsr_read4(OCP85XX_COREDISR);
-       cpuid = pc->pc_cpuid;
-
-       if ((reg & cpuid) != 0) {
-               printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
-               return (-1);
+       if (mpc85xx_is_qoriq()) {
+               reg = ccsr_read4(OCP85XX_COREDISR);
+               cpuid = pc->pc_cpuid;
+
+               if ((reg & (1 << cpuid)) != 0) {
+                   printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid);
+                   return (-1);
+               }
+
+               brr = OCP85XX_BRR;
+       } else {
+               brr = OCP85XX_EEBPCR;
+               cpuid = pc->pc_cpuid + 24;
        }
-
-       brr = OCP85XX_BRR;
-#else /* QORIQ_DPAA */
-       brr = OCP85XX_EEBPCR;
-       cpuid = pc->pc_cpuid + 24;
-#endif
        bp_kernload = kernload;
+
        reg = ccsr_read4(brr);
        if ((reg & (1 << cpuid)) != 0) {
                printf("SMP: CPU %d already out of hold-off state!\n",
@@ -358,55 +359,52 @@ mpc85xx_smp_start_cpu(platform_t plat, s
        bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload;
        KASSERT((bptr & 0xfff) == 0,
            ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr));
-#ifdef QORIQ_DPAA
-
-       /*
-        * Read DDR controller configuration to select proper BPTR target ID.
-        *
-        * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
-        * interleaving. If this bit is set, we have to use
-        * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs,
-        * this bit is reserved and always 0.
-        */
-
-       reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
-       if (reg & (1 << 29))
-               tgt = OCP85XX_TGTIF_RAM_INTL;
-       else
-               tgt = OCP85XX_TGTIF_RAM1;
-
-       /*
-        * Set BSTR to the physical address of the boot page
-        */
-       ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
-       ccsr_write4(OCP85XX_BSTRL, bptr);
-       ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
-           (tgt << OCP85XX_TRGT_SHIFT) | (ffsl(PAGE_SIZE) - 2));
-
-       /* Read back OCP85XX_BSTAR to synchronize write */
-       ccsr_read4(OCP85XX_BSTAR);
-
-       /*
-        * Enable and configure time base on new CPU.
-        */
-
-       /* Set TB clock source to platform clock / 32 */
-       reg = ccsr_read4(CCSR_CTBCKSELR);
-       ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
-
-       /* Enable TB */
-       reg = ccsr_read4(CCSR_CTBENR);
-       ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
-#else
-
-       /*
-        * Set BPTR to the physical address of the boot page
-        */
-       bptr = (bptr >> 12) | 0x80000000u;
-       ccsr_write4(OCP85XX_BPTR, bptr);
-       __asm __volatile("isync; msync");
-
-#endif /* QORIQ_DPAA */
+       if (mpc85xx_is_qoriq()) {
+               /*
+                * Read DDR controller configuration to select proper BPTR 
target ID.
+                *
+                * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers
+                * interleaving. If this bit is set, we have to use
+                * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ 
DPAA SoCs,
+                * this bit is reserved and always 0.
+                */
+
+               reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG);
+               if (reg & (1 << 29))
+                       tgt = OCP85XX_TGTIF_RAM_INTL;
+               else
+                       tgt = OCP85XX_TGTIF_RAM1;
+
+               /*
+                * Set BSTR to the physical address of the boot page
+                */
+               ccsr_write4(OCP85XX_BSTRH, bptr >> 32);
+               ccsr_write4(OCP85XX_BSTRL, bptr);
+               ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK |
+                   (tgt << OCP85XX_TRGT_SHIFT_QORIQ) | (ffsl(PAGE_SIZE) - 2));
+
+               /* Read back OCP85XX_BSTAR to synchronize write */
+               ccsr_read4(OCP85XX_BSTAR);
+
+               /*
+                * Enable and configure time base on new CPU.
+                */
+
+               /* Set TB clock source to platform clock / 32 */
+               reg = ccsr_read4(CCSR_CTBCKSELR);
+               ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid));
+
+               /* Enable TB */
+               reg = ccsr_read4(CCSR_CTBENR);
+               ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid));
+       } else {
+               /*
+                * Set BPTR to the physical address of the boot page
+                */
+               bptr = (bptr >> 12) | 0x80000000u;
+               ccsr_write4(OCP85XX_BPTR, bptr);
+               __asm __volatile("isync; msync");
+       }
 
        /*
         * Release AP from hold-off state
@@ -424,15 +422,14 @@ mpc85xx_smp_start_cpu(platform_t plat, s
         * address (= 0xfffff000) isn't permanently remapped and thus not
         * usable otherwise.
         */
-#ifdef QORIQ_DPAA
-       ccsr_write4(OCP85XX_BSTAR, 0);
-#else
-       ccsr_write4(OCP85XX_BPTR, 0);
-#endif
+       if (mpc85xx_is_qoriq())
+               ccsr_write4(OCP85XX_BSTAR, 0);
+       else
+               ccsr_write4(OCP85XX_BPTR, 0);
        __asm __volatile("isync; msync");
 
        if (!pc->pc_awake)
-               printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
+               panic("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid);
        return ((pc->pc_awake) ? 0 : EBUSY);
 #else
        /* No SMP support */
@@ -469,33 +466,32 @@ mpc85xx_reset(platform_t plat)
 static void
 mpc85xx_idle(platform_t plat, int cpu)
 {
-#ifdef QORIQ_DPAA
        uint32_t reg;
 
-       reg = ccsr_read4(OCP85XX_RCPM_CDOZCR);
-       ccsr_write4(OCP85XX_RCPM_CDOZCR, reg | (1 << cpu));
-       ccsr_read4(OCP85XX_RCPM_CDOZCR);
-#else
-       register_t msr;
-
-       msr = mfmsr();
-       /* Freescale E500 core RM section 6.4.1. */
-       __asm __volatile("msync; mtmsr %0; isync" ::
-           "r" (msr | PSL_WE));
-#endif
+       if (mpc85xx_is_qoriq()) {
+               reg = ccsr_read4(OCP85XX_RCPM_CDOZCR);
+               ccsr_write4(OCP85XX_RCPM_CDOZCR, reg | (1 << cpu));
+               ccsr_read4(OCP85XX_RCPM_CDOZCR);
+       } else {
+               reg = mfmsr();
+               /* Freescale E500 core RM section 6.4.1. */
+               __asm __volatile("msync; mtmsr %0; isync" ::
+                   "r" (reg | PSL_WE));
+       }
 }
 
 static int
 mpc85xx_idle_wakeup(platform_t plat, int cpu)
 {
-#ifdef QORIQ_DPAA
        uint32_t reg;
 
-       reg = ccsr_read4(OCP85XX_RCPM_CDOZCR);
-       ccsr_write4(OCP85XX_RCPM_CDOZCR, reg & ~(1 << cpu));
-       ccsr_read4(OCP85XX_RCPM_CDOZCR);
+       if (mpc85xx_is_qoriq()) {
+               reg = ccsr_read4(OCP85XX_RCPM_CDOZCR);
+               ccsr_write4(OCP85XX_RCPM_CDOZCR, reg & ~(1 << cpu));
+               ccsr_read4(OCP85XX_RCPM_CDOZCR);
+
+               return (1);
+       }
 
-       return (1);
-#endif
        return (0);
 }
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