Author: andrew
Date: Wed Jun 13 12:17:11 2018
New Revision: 335052
URL: https://svnweb.freebsd.org/changeset/base/335052

Log:
  Rename the ThunderX CPU identification macros to include the X. This is the
  name people know the product by, and is consistent with the later SoC ID
  macros.
  
  Sponsored by: DARPA, AFRL

Modified:
  head/sys/arm64/arm64/gic_v3.c
  head/sys/arm64/arm64/identcpu.c
  head/sys/arm64/cavium/thunder_pcie_common.c
  head/sys/arm64/cavium/thunder_pcie_fdt.c
  head/sys/arm64/include/cpu.h

Modified: head/sys/arm64/arm64/gic_v3.c
==============================================================================
--- head/sys/arm64/arm64/gic_v3.c       Wed Jun 13 11:58:41 2018        
(r335051)
+++ head/sys/arm64/arm64/gic_v3.c       Wed Jun 13 12:17:11 2018        
(r335052)
@@ -418,7 +418,7 @@ arm_gic_v3_intr(void *arg)
        pic = sc->gic_pic;
 
        while (1) {
-               if (CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1) {
+               if (CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1) {
                        /*
                         * Hardware:            Cavium ThunderX
                         * Chip revision:       Pass 1.0 (early version)

Modified: head/sys/arm64/arm64/identcpu.c
==============================================================================
--- head/sys/arm64/arm64/identcpu.c     Wed Jun 13 11:58:41 2018        
(r335051)
+++ head/sys/arm64/arm64/identcpu.c     Wed Jun 13 12:17:11 2018        
(r335052)
@@ -133,7 +133,7 @@ static const struct cpu_parts cpu_parts_arm[] = {
 };
 /* Cavium */
 static const struct cpu_parts cpu_parts_cavium[] = {
-       { CPU_PART_THUNDER, "Thunder" },
+       { CPU_PART_THUNDERX, "ThunderX" },
        CPU_PART_NONE,
 };
 
@@ -212,11 +212,11 @@ print_cpu_features(u_int cpu)
         * https://lkml.org/lkml/2016/8/4/722
         */
        /*
-        * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 on its own also
+        * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 on its own also
         * triggers on pass 2.0+.
         */
        if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 &&
-           CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1)
+           CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1)
                printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known "
                    "hardware bugs that may cause the incorrect operation of "
                    "atomic operations.\n");

Modified: head/sys/arm64/cavium/thunder_pcie_common.c
==============================================================================
--- head/sys/arm64/cavium/thunder_pcie_common.c Wed Jun 13 11:58:41 2018        
(r335051)
+++ head/sys/arm64/cavium/thunder_pcie_common.c Wed Jun 13 12:17:11 2018        
(r335052)
@@ -159,7 +159,7 @@ thunder_pcie_identify_ecam(device_t dev, int *ecam)
 
        /* Check if we're running on Cavium ThunderX */
        if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
-           CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0))
+           CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0))
                return (EINVAL);
 
        start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);

Modified: head/sys/arm64/cavium/thunder_pcie_fdt.c
==============================================================================
--- head/sys/arm64/cavium/thunder_pcie_fdt.c    Wed Jun 13 11:58:41 2018        
(r335051)
+++ head/sys/arm64/cavium/thunder_pcie_fdt.c    Wed Jun 13 12:17:11 2018        
(r335052)
@@ -97,7 +97,7 @@ thunder_pcie_fdt_probe(device_t dev)
 
        /* Check if we're running on Cavium ThunderX */
        if (!CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
-           CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0))
+           CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, 0))
                return (ENXIO);
 
        if (!ofw_bus_status_okay(dev))

Modified: head/sys/arm64/include/cpu.h
==============================================================================
--- head/sys/arm64/include/cpu.h        Wed Jun 13 11:58:41 2018        
(r335051)
+++ head/sys/arm64/include/cpu.h        Wed Jun 13 12:17:11 2018        
(r335052)
@@ -89,13 +89,13 @@
 #define        CPU_PART_CORTEX_A75     0xD0A
 
 /* Cavium Part numbers */
-#define        CPU_PART_THUNDER        0x0A1
+#define        CPU_PART_THUNDERX       0x0A1
 #define        CPU_PART_THUNDERX_81XX  0x0A2
 #define        CPU_PART_THUNDERX_83XX  0x0A3
 #define        CPU_PART_THUNDERX2      0x0AF
 
-#define        CPU_REV_THUNDER_1_0     0x00
-#define        CPU_REV_THUNDER_1_1     0x01
+#define        CPU_REV_THUNDERX_1_0    0x00
+#define        CPU_REV_THUNDERX_1_1    0x01
 
 #define        CPU_IMPL(midr)  (((midr) >> 24) & 0xff)
 #define        CPU_PART(midr)  (((midr) >> 4) & 0xfff)
@@ -137,13 +137,13 @@
  * Revision(s):        Pass 1.0, Pass 1.1
  */
 #ifdef THUNDERX_PASS_1_1_ERRATA
-#define        CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1                             
\
+#define        CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1                            
\
     (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK,           \
-    CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_0) ||      \
+    CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) ||    \
     CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK,            \
-    CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_1))
+    CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1))
 #else
-#define        CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1     0
+#define        CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1    0
 #endif
 
 
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