On Fri, Jul 13, 2018 at 07:42:59PM +0000, Mark Johnston wrote: > Author: markj > Date: Fri Jul 13 19:42:59 2018 > New Revision: 336257 > URL: https://svnweb.freebsd.org/changeset/base/336257 > > Log: > Define the MSR used to fetch the current microcode patch level on AMD. > > It is defined in the AMD family 17h register reference. > > MFC after: 3 days > Sponsored by: The FreeBSD Foundation > > Modified: > head/sys/x86/include/specialreg.h > > Modified: head/sys/x86/include/specialreg.h > ============================================================================== > --- head/sys/x86/include/specialreg.h Fri Jul 13 18:58:37 2018 > (r336256) > +++ head/sys/x86/include/specialreg.h Fri Jul 13 19:42:59 2018 > (r336257) > @@ -973,6 +973,7 @@ > #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range > enable */ > > /* AMD64 MSR's */ > +#define MSR_PATCH_LEVEL 0x0000008b /* microcode revision number */ This register is called MSR_BIOS_SIGN. It is defined for Intel as well.
> #define MSR_EFER 0xc0000080 /* extended features */ > #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL > target/cs/ss */ > #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip > */ _______________________________________________ [email protected] mailing list https://lists.freebsd.org/mailman/listinfo/svn-src-all To unsubscribe, send any mail to "[email protected]"
