Author: kib
Date: Fri Nov 16 21:27:11 2018
New Revision: 340487
URL: https://svnweb.freebsd.org/changeset/base/340487
Log:
Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068.
SDM rev. 068 was released yesterday and it contains the description of
the MSR 0x10a IA32_ARCH_CAP. This change adds symbolic definitions for
all bits present in the document, and decode them in the CPU
identification lines printed on boot.
But also, the document defines SSB_NO as bit 4, while FreeBSD used but
2 to detect the need to work-around Speculative Store Bypass
issue. Change code to use the bit from SDM.
Similarly, the document describes bit 3 as an indicator that L1TF
issue is not present, in particular, no L1D flush is needed on
VMENTRY. We used RDCL_NO to avoid flushing, and again I changed the
code to follow new spec from SDM.
In fact my Apollo Lake machine with latest ucode shows this:
IA32_ARCH_CAPS=0x19<RDCL_NO,SKIP_L1DFL_VME,SSB_NO>
Reviewed by: bwidawsk
Sponsored by: The FreeBSD Foundation
MFC after: 3 days
Differential revision: https://reviews.freebsd.org/D18006
Modified:
head/sys/amd64/vmm/intel/vmx.c
head/sys/x86/include/specialreg.h
head/sys/x86/x86/cpu_machdep.c
head/sys/x86/x86/identcpu.c
Modified: head/sys/amd64/vmm/intel/vmx.c
==============================================================================
--- head/sys/amd64/vmm/intel/vmx.c Fri Nov 16 19:08:52 2018
(r340486)
+++ head/sys/amd64/vmm/intel/vmx.c Fri Nov 16 21:27:11 2018
(r340487)
@@ -814,7 +814,8 @@ vmx_init(int ipinum)
return (error);
}
- guest_l1d_flush = (cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) == 0;
+ guest_l1d_flush = (cpu_ia32_arch_caps &
+ IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY) == 0;
TUNABLE_INT_FETCH("hw.vmm.l1d_flush", &guest_l1d_flush);
/*
Modified: head/sys/x86/include/specialreg.h
==============================================================================
--- head/sys/x86/include/specialreg.h Fri Nov 16 19:08:52 2018
(r340486)
+++ head/sys/x86/include/specialreg.h Fri Nov 16 21:27:11 2018
(r340487)
@@ -434,7 +434,9 @@
/* MSR IA32_ARCH_CAP(ABILITIES) bits */
#define IA32_ARCH_CAP_RDCL_NO 0x00000001
#define IA32_ARCH_CAP_IBRS_ALL 0x00000002
-#define IA32_ARCH_CAP_SSBD_NO 0x00000004
+#define IA32_ARCH_CAP_RSBA 0x00000004
+#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
+#define IA32_ARCH_CAP_SSB_NO 0x00000010
/*
* CPUID manufacturers identifiers
Modified: head/sys/x86/x86/cpu_machdep.c
==============================================================================
--- head/sys/x86/x86/cpu_machdep.c Fri Nov 16 19:08:52 2018
(r340486)
+++ head/sys/x86/x86/cpu_machdep.c Fri Nov 16 21:27:11 2018
(r340487)
@@ -891,7 +891,7 @@ hw_ssb_recalculate(bool all_cpus)
hw_ssb_set(true, all_cpus);
break;
case 2: /* auto */
- hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSBD_NO) != 0 ?
+ hw_ssb_set((cpu_ia32_arch_caps & IA32_ARCH_CAP_SSB_NO) != 0 ?
false : true, all_cpus);
break;
}
Modified: head/sys/x86/x86/identcpu.c
==============================================================================
--- head/sys/x86/x86/identcpu.c Fri Nov 16 19:08:52 2018 (r340486)
+++ head/sys/x86/x86/identcpu.c Fri Nov 16 21:27:11 2018 (r340487)
@@ -1014,6 +1014,9 @@ printcpuinfo(void)
"\020"
"\001RDCL_NO"
"\002IBRS_ALL"
+ "\003RSBA"
+ "\004SKIP_L1DFL_VME"
+ "\005SSB_NO"
);
}
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