Author: mw
Date: Thu Dec 20 01:05:09 2018
New Revision: 342271
URL: https://svnweb.freebsd.org/changeset/base/342271
Log:
Fix obtaining RSP address in TPM CRB for non-amd64 platforms
On amd64 the RSP address can be read in single 8-byte transaction,
which is obviously not possible on 32-bit platforms. Fix that
by performing 2 4-byte read on them.
Obtained from: Semihalf
Sponsored by: Stormshield
Modified:
head/sys/dev/tpm/tpm20.h
head/sys/dev/tpm/tpm_crb.c
Modified: head/sys/dev/tpm/tpm20.h
==============================================================================
--- head/sys/dev/tpm/tpm20.h Thu Dec 20 01:00:21 2018 (r342270)
+++ head/sys/dev/tpm/tpm20.h Thu Dec 20 01:05:09 2018 (r342271)
@@ -153,12 +153,14 @@ RD4(struct tpm_sc *sc, bus_size_t off)
return (bus_read_4(sc->mem_res, off));
}
+#ifdef __amd64__
static inline uint64_t
RD8(struct tpm_sc *sc, bus_size_t off)
{
return (bus_read_8(sc->mem_res, off));
}
+#endif
static inline void
WR1(struct tpm_sc *sc, bus_size_t off, uint8_t val)
{
Modified: head/sys/dev/tpm/tpm_crb.c
==============================================================================
--- head/sys/dev/tpm/tpm_crb.c Thu Dec 20 01:00:21 2018 (r342270)
+++ head/sys/dev/tpm/tpm_crb.c Thu Dec 20 01:05:09 2018 (r342271)
@@ -50,6 +50,7 @@ __FBSDID("$FreeBSD$");
#define TPM_CRB_CTRL_CMD_HADDR 0x60
#define TPM_CRB_CTRL_RSP_SIZE 0x64
#define TPM_CRB_CTRL_RSP_ADDR 0x68
+#define TPM_CRB_CTRL_RSP_HADDR 0x6c
#define TPM_CRB_DATA_BUFFER 0x80
#define TPM_LOC_STATE_ESTB BIT(0)
@@ -188,7 +189,12 @@ tpmcrb_attach(device_t dev)
* addr is stored in two 4 byte neighboring registers, whereas RSP is
* stored in a single 8 byte one.
*/
+#ifdef __amd64__
crb_sc->rsp_off = RD8(sc, TPM_CRB_CTRL_RSP_ADDR);
+#else
+ crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR);
+ crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32);
+#endif
crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR);
crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32);
crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE);
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