Author: jhibbits
Date: Sat Feb 16 04:38:34 2019
New Revision: 344203
URL: https://svnweb.freebsd.org/changeset/base/344203
Log:
powerpc/booke: depessimize MAS register updates
We only need to isync before we actually use the MAS registers, so before and
after the TLB read/write/sync/search operations.
MFC after: 2 weeks
Modified:
head/sys/powerpc/booke/pmap.c
Modified: head/sys/powerpc/booke/pmap.c
==============================================================================
--- head/sys/powerpc/booke/pmap.c Sat Feb 16 04:16:10 2019
(r344202)
+++ head/sys/powerpc/booke/pmap.c Sat Feb 16 04:38:34 2019
(r344203)
@@ -3911,29 +3911,23 @@ tlb1_write_entry_int(void *arg)
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx);
mtspr(SPR_MAS0, mas0);
- __asm __volatile("isync");
mtspr(SPR_MAS1, args->e->mas1);
- __asm __volatile("isync");
mtspr(SPR_MAS2, args->e->mas2);
- __asm __volatile("isync");
mtspr(SPR_MAS3, args->e->mas3);
- __asm __volatile("isync");
switch ((mfpvr() >> 16) & 0xFFFF) {
case FSL_E500mc:
case FSL_E5500:
case FSL_E6500:
mtspr(SPR_MAS8, 0);
- __asm __volatile("isync");
/* FALLTHROUGH */
case FSL_E500v2:
mtspr(SPR_MAS7, args->e->mas7);
- __asm __volatile("isync");
break;
default:
break;
}
- __asm __volatile("tlbwe; isync; msync");
+ __asm __volatile("isync; tlbwe; isync; msync");
}
@@ -4376,7 +4370,6 @@ tid_flush(tlbtid_t tid)
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
mtspr(SPR_MAS0, mas0);
- __asm __volatile("isync");
mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
mtspr(SPR_MAS2, mas2);
@@ -4453,7 +4446,6 @@ DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
mtspr(SPR_MAS0, mas0);
- __asm __volatile("isync");
mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
mtspr(SPR_MAS2, mas2);
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