> On Feb 21, 2019, at 6:10 AM, Alexander Motin <m...@freebsd.org> wrote:
>
> Author: mav
> Date: Thu Feb 21 14:10:14 2019
> New Revision: 344437
> URL: https://svnweb.freebsd.org/changeset/base/344437
>
> Log:
> Allow I/OAT of present Xeon E5/E7 to work thorugh PLX NTB.
>
> Its a hack, we can't know/list all DMA engines, but this covers all
> I/OAT of Xeon E5/E7 at least from Sandy Bridge till Skylake I saw.
>
> MFC after: 1 week
> Sponsored by: iXsystems, Inc.
>
> Modified:
> head/sys/dev/ntb/ntb_hw/ntb_hw_plx.c
>
> Modified: head/sys/dev/ntb/ntb_hw/ntb_hw_plx.c
> ==============================================================================
> --- head/sys/dev/ntb/ntb_hw/ntb_hw_plx.c Thu Feb 21 12:13:27 2019
> (r344436)
> +++ head/sys/dev/ntb/ntb_hw/ntb_hw_plx.c Thu Feb 21 14:10:14 2019
> (r344437)
> @@ -202,16 +202,24 @@ ntb_plx_init(device_t dev)
> if (sc->alut)
> PNTX_WRITE(sc, 0xc94, 0);
>
> - /* Enable Link Interface LUT entries 0/1 for peer 0/1. */
> - PNTX_WRITE(sc, 0xdb4, 0x00090001);
> + /* Enable all Link Interface LUT entries for peer. */
> + for (i = 0; i < 32; i += 2) {
Is `32` written down in the NTB spec somewhere? Should it be a #define,
or should it be programmatically adjusted based on the CPU?
Thank you!
-Enji
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