Author: andrew
Date: Mon Mar 25 18:02:04 2019
New Revision: 345510
URL: https://svnweb.freebsd.org/changeset/base/345510
Log:
Sort printing of the ID registers on arm64 to be identical to the
documentation. This will simplify checking new fields when they are added.
MFC after: 2 weeks
Sponsored by: DARPA, AFRL
Modified:
head/sys/arm64/arm64/identcpu.c
Modified: head/sys/arm64/arm64/identcpu.c
==============================================================================
--- head/sys/arm64/arm64/identcpu.c Mon Mar 25 17:45:47 2019
(r345509)
+++ head/sys/arm64/arm64/identcpu.c Mon Mar 25 18:02:04 2019
(r345510)
@@ -494,63 +494,68 @@ print_cpu_features(u_int cpu)
printed = 0;
sbuf_printf(sb, " Instruction Set Attributes 0 = <");
- switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_RDM_NONE:
+ switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_DP_NONE:
break;
- case ID_AA64ISAR0_RDM_IMPL:
- sbuf_printf(sb, "%sRDM", SEP_STR);
+ case ID_AA64ISAR0_DP_IMPL:
+ sbuf_printf(sb, "%sDotProd", SEP_STR);
break;
default:
- sbuf_printf(sb, "%sUnknown RDM", SEP_STR);
+ sbuf_printf(sb, "%sUnknown DP", SEP_STR);
+ break;
}
- switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_ATOMIC_NONE:
+ switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SM4_NONE:
break;
- case ID_AA64ISAR0_ATOMIC_IMPL:
- sbuf_printf(sb, "%sAtomic", SEP_STR);
+ case ID_AA64ISAR0_SM4_IMPL:
+ sbuf_printf(sb, "%sSM4", SEP_STR);
break;
default:
- sbuf_printf(sb, "%sUnknown Atomic", SEP_STR);
+ sbuf_printf(sb, "%sUnknown SM4", SEP_STR);
+ break;
}
- switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_AES_NONE:
+ switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SM3_NONE:
break;
- case ID_AA64ISAR0_AES_BASE:
- sbuf_printf(sb, "%sAES", SEP_STR);
+ case ID_AA64ISAR0_SM3_IMPL:
+ sbuf_printf(sb, "%sSM3", SEP_STR);
break;
- case ID_AA64ISAR0_AES_PMULL:
- sbuf_printf(sb, "%sAES+PMULL", SEP_STR);
- break;
default:
- sbuf_printf(sb, "%sUnknown AES", SEP_STR);
+ sbuf_printf(sb, "%sUnknown SM3", SEP_STR);
break;
}
- switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_SHA1_NONE:
+ switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SHA3_NONE:
break;
- case ID_AA64ISAR0_SHA1_BASE:
- sbuf_printf(sb, "%sSHA1", SEP_STR);
+ case ID_AA64ISAR0_SHA3_IMPL:
+ sbuf_printf(sb, "%sSHA3", SEP_STR);
break;
default:
- sbuf_printf(sb, "%sUnknown SHA1", SEP_STR);
+ sbuf_printf(sb, "%sUnknown SHA3", SEP_STR);
break;
}
- switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_SHA2_NONE:
+ switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_RDM_NONE:
break;
- case ID_AA64ISAR0_SHA2_BASE:
- sbuf_printf(sb, "%sSHA2", SEP_STR);
+ case ID_AA64ISAR0_RDM_IMPL:
+ sbuf_printf(sb, "%sRDM", SEP_STR);
break;
- case ID_AA64ISAR0_SHA2_512:
- sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR);
- break;
default:
- sbuf_printf(sb, "%sUnknown SHA2", SEP_STR);
+ sbuf_printf(sb, "%sUnknown RDM", SEP_STR);
+ }
+
+ switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_ATOMIC_NONE:
break;
+ case ID_AA64ISAR0_ATOMIC_IMPL:
+ sbuf_printf(sb, "%sAtomic", SEP_STR);
+ break;
+ default:
+ sbuf_printf(sb, "%sUnknown Atomic", SEP_STR);
}
switch (ID_AA64ISAR0_CRC32(cpu_desc[cpu].id_aa64isar0)) {
@@ -564,47 +569,42 @@ print_cpu_features(u_int cpu)
break;
}
- switch (ID_AA64ISAR0_SHA3(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_SHA3_NONE:
+ switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SHA2_NONE:
break;
- case ID_AA64ISAR0_SHA3_IMPL:
- sbuf_printf(sb, "%sSHA3", SEP_STR);
+ case ID_AA64ISAR0_SHA2_BASE:
+ sbuf_printf(sb, "%sSHA2", SEP_STR);
break;
- default:
- sbuf_printf(sb, "%sUnknown SHA3", SEP_STR);
+ case ID_AA64ISAR0_SHA2_512:
+ sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR);
break;
- }
-
- switch (ID_AA64ISAR0_SM3(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_SM3_NONE:
- break;
- case ID_AA64ISAR0_SM3_IMPL:
- sbuf_printf(sb, "%sSM3", SEP_STR);
- break;
default:
- sbuf_printf(sb, "%sUnknown SM3", SEP_STR);
+ sbuf_printf(sb, "%sUnknown SHA2", SEP_STR);
break;
}
- switch (ID_AA64ISAR0_SM4(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_SM4_NONE:
+ switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_SHA1_NONE:
break;
- case ID_AA64ISAR0_SM4_IMPL:
- sbuf_printf(sb, "%sSM4", SEP_STR);
+ case ID_AA64ISAR0_SHA1_BASE:
+ sbuf_printf(sb, "%sSHA1", SEP_STR);
break;
default:
- sbuf_printf(sb, "%sUnknown SM4", SEP_STR);
+ sbuf_printf(sb, "%sUnknown SHA1", SEP_STR);
break;
}
- switch (ID_AA64ISAR0_DP(cpu_desc[cpu].id_aa64isar0)) {
- case ID_AA64ISAR0_DP_NONE:
+ switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) {
+ case ID_AA64ISAR0_AES_NONE:
break;
- case ID_AA64ISAR0_DP_IMPL:
- sbuf_printf(sb, "%sDotProd", SEP_STR);
+ case ID_AA64ISAR0_AES_BASE:
+ sbuf_printf(sb, "%sAES", SEP_STR);
break;
+ case ID_AA64ISAR0_AES_PMULL:
+ sbuf_printf(sb, "%sAES+PMULL", SEP_STR);
+ break;
default:
- sbuf_printf(sb, "%sUnknown DP", SEP_STR);
+ sbuf_printf(sb, "%sUnknown AES", SEP_STR);
break;
}
@@ -868,17 +868,6 @@ print_cpu_features(u_int cpu)
break;
}
- switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) {
- case ID_AA64MMFR0_TGRAN16_NONE:
- break;
- case ID_AA64MMFR0_TGRAN16_IMPL:
- sbuf_printf(sb, "%s16k Granule", SEP_STR);
- break;
- default:
- sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR);
- break;
- }
-
switch (ID_AA64MMFR0_TGRAN64(cpu_desc[cpu].id_aa64mmfr0)) {
case ID_AA64MMFR0_TGRAN64_NONE:
break;
@@ -890,14 +879,14 @@ print_cpu_features(u_int cpu)
break;
}
- switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) {
- case ID_AA64MMFR0_BIGEND_FIXED:
+ switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) {
+ case ID_AA64MMFR0_TGRAN16_NONE:
break;
- case ID_AA64MMFR0_BIGEND_MIXED:
- sbuf_printf(sb, "%sMixedEndian", SEP_STR);
+ case ID_AA64MMFR0_TGRAN16_IMPL:
+ sbuf_printf(sb, "%s16k Granule", SEP_STR);
break;
default:
- sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR);
+ sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR);
break;
}
@@ -920,6 +909,17 @@ print_cpu_features(u_int cpu)
break;
default:
sbuf_printf(sb, "%sUnknown S/NS Mem", SEP_STR);
+ break;
+ }
+
+ switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) {
+ case ID_AA64MMFR0_BIGEND_FIXED:
+ break;
+ case ID_AA64MMFR0_BIGEND_MIXED:
+ sbuf_printf(sb, "%sMixedEndian", SEP_STR);
+ break;
+ default:
+ sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR);
break;
}
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