Author: kib
Date: Tue Apr 16 17:16:18 2019
New Revision: 346284
URL: https://svnweb.freebsd.org/changeset/base/346284
Log:
MFC r346062:
pci_cfgreg.c: Use io port config access for early boot time.
PR: 236838
Modified:
stable/12/sys/amd64/pci/pci_cfgreg.c
stable/12/sys/i386/pci/pci_cfgreg.c
stable/12/sys/x86/include/pci_cfgreg.h
stable/12/sys/x86/x86/legacy.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/amd64/pci/pci_cfgreg.c
==============================================================================
--- stable/12/sys/amd64/pci/pci_cfgreg.c Tue Apr 16 17:12:27 2019
(r346283)
+++ stable/12/sys/amd64/pci/pci_cfgreg.c Tue Apr 16 17:16:18 2019
(r346284)
@@ -44,12 +44,6 @@ __FBSDID("$FreeBSD$");
#include <vm/pmap.h>
#include <machine/pci_cfgreg.h>
-enum {
- CFGMECH_NONE = 0,
- CFGMECH_1,
- CFGMECH_PCIE,
-};
-
static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
int bytes);
static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
@@ -61,7 +55,13 @@ static void pcireg_cfgwrite(int bus, int slot, int fun
SYSCTL_DECL(_hw_pci);
-static int cfgmech;
+/*
+ * For amd64 we assume that type 1 I/O port-based access always works.
+ * If an ACPI MCFG table exists, pcie_cfgregopen() will be called to
+ * switch to memory-mapped access.
+ */
+int cfgmech = CFGMECH_1;
+
static vm_offset_t pcie_base;
static int pcie_minbus, pcie_maxbus;
static uint32_t pcie_badslots;
@@ -71,47 +71,10 @@ static int mcfg_enable = 1;
SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
"Enable support for PCI-e memory mapped config access");
-/*
- * Initialise access to PCI configuration space
- */
int
pci_cfgregopen(void)
{
- uint64_t pciebar;
- uint16_t did, vid;
- if (cfgmech != CFGMECH_NONE)
- return (1);
- cfgmech = CFGMECH_1;
-
- /*
- * Grope around in the PCI config space to see if this is a
- * chipset that is capable of doing memory-mapped config cycles.
- * This also implies that it can do PCIe extended config cycles.
- */
-
- /* Check for supported chipsets */
- vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
- did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
- switch (vid) {
- case 0x8086:
- switch (did) {
- case 0x3590:
- case 0x3592:
- /* Intel 7520 or 7320 */
- pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
- pcie_cfgregopen(pciebar, 0, 255);
- break;
- case 0x2580:
- case 0x2584:
- case 0x2590:
- /* Intel 915, 925, or 915GM */
- pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
- pcie_cfgregopen(pciebar, 0, 255);
- break;
- }
- }
-
return (1);
}
@@ -135,9 +98,6 @@ pci_cfgregread(int bus, int slot, int func, int reg, i
{
uint32_t line;
- if (cfgmech == CFGMECH_NONE)
- return (0xffffffff);
-
/*
* Some BIOS writers seem to want to ignore the spec and put
* 0 in the intline rather than 255 to indicate none. Some use
@@ -161,9 +121,6 @@ pci_cfgregread(int bus, int slot, int func, int reg, i
void
pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int
bytes)
{
-
- if (cfgmech == CFGMECH_NONE)
- return;
if (cfgmech == CFGMECH_PCIE &&
(bus >= pcie_minbus && bus <= pcie_maxbus) &&
Modified: stable/12/sys/i386/pci/pci_cfgreg.c
==============================================================================
--- stable/12/sys/i386/pci/pci_cfgreg.c Tue Apr 16 17:12:27 2019
(r346283)
+++ stable/12/sys/i386/pci/pci_cfgreg.c Tue Apr 16 17:16:18 2019
(r346284)
@@ -64,20 +64,13 @@ struct pcie_cfg_elem {
vm_paddr_t papage;
};
-enum {
- CFGMECH_NONE = 0,
- CFGMECH_1,
- CFGMECH_2,
- CFGMECH_PCIE,
-};
-
SYSCTL_DECL(_hw_pci);
static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
static uint64_t pcie_base;
static int pcie_minbus, pcie_maxbus;
static uint32_t pcie_badslots;
-static int cfgmech;
+int cfgmech;
static int devmax;
static struct mtx pcicfg_mtx;
static int mcfg_enable = 1;
@@ -136,10 +129,8 @@ pcibios_get_version(void)
int
pci_cfgregopen(void)
{
- static int opened = 0;
- uint64_t pciebar;
- u_int16_t vid, did;
- u_int16_t v;
+ uint16_t v;
+ static int opened = 0;
if (opened)
return (1);
@@ -158,38 +149,7 @@ pci_cfgregopen(void)
if (v >= 0x0210)
pci_pir_open();
- if (cfgmech == CFGMECH_PCIE)
- return (1);
-
- /*
- * Grope around in the PCI config space to see if this is a
- * chipset that is capable of doing memory-mapped config cycles.
- * This also implies that it can do PCIe extended config cycles.
- */
-
- /* Check for supported chipsets */
- vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
- did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
- switch (vid) {
- case 0x8086:
- switch (did) {
- case 0x3590:
- case 0x3592:
- /* Intel 7520 or 7320 */
- pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
- pcie_cfgregopen(pciebar, 0, 255);
- break;
- case 0x2580:
- case 0x2584:
- case 0x2590:
- /* Intel 915, 925, or 915GM */
- pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
- pcie_cfgregopen(pciebar, 0, 255);
- break;
- }
- }
-
- return(1);
+ return (1);
}
static uint32_t
Modified: stable/12/sys/x86/include/pci_cfgreg.h
==============================================================================
--- stable/12/sys/x86/include/pci_cfgreg.h Tue Apr 16 17:12:27 2019
(r346283)
+++ stable/12/sys/x86/include/pci_cfgreg.h Tue Apr 16 17:16:18 2019
(r346284)
@@ -48,6 +48,15 @@
#define CONF2_ENABLE_CHK 0x0e
#define CONF2_ENABLE_RES 0x0e
+enum {
+ CFGMECH_NONE = 0,
+ CFGMECH_1,
+ CFGMECH_2,
+ CFGMECH_PCIE,
+};
+
+extern int cfgmech;
+
rman_res_t hostb_alloc_start(int type, rman_res_t start, rman_res_t end,
rman_res_t count);
int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
int pci_cfgregopen(void);
Modified: stable/12/sys/x86/x86/legacy.c
==============================================================================
--- stable/12/sys/x86/x86/legacy.c Tue Apr 16 17:12:27 2019
(r346283)
+++ stable/12/sys/x86/x86/legacy.c Tue Apr 16 17:16:18 2019
(r346284)
@@ -46,8 +46,10 @@ __FBSDID("$FreeBSD$");
#include <sys/pcpu.h>
#include <sys/rman.h>
#include <sys/smp.h>
+#include <dev/pci/pcireg.h>
#include <machine/clock.h>
+#include <machine/pci_cfgreg.h>
#include <machine/resource.h>
#include <x86/legacyvar.h>
@@ -111,10 +113,52 @@ legacy_probe(device_t dev)
return (0);
}
+/*
+ * Grope around in the PCI config space to see if this is a chipset
+ * that is capable of doing memory-mapped config cycles. This also
+ * implies that it can do PCIe extended config cycles.
+ */
+static void
+legacy_pci_cfgregopen(device_t dev)
+{
+ uint64_t pciebar;
+ u_int16_t did, vid;
+
+ if (cfgmech == CFGMECH_NONE || cfgmech == CFGMECH_PCIE)
+ return;
+
+ /* Check for supported chipsets */
+ vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
+ did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
+ switch (vid) {
+ case 0x8086:
+ switch (did) {
+ case 0x3590:
+ case 0x3592:
+ /* Intel 7520 or 7320 */
+ pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
+ pcie_cfgregopen(pciebar, 0, 255);
+ break;
+ case 0x2580:
+ case 0x2584:
+ case 0x2590:
+ /* Intel 915, 925, or 915GM */
+ pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
+ pcie_cfgregopen(pciebar, 0, 255);
+ break;
+ }
+ }
+
+ if (bootverbose && cfgmech == CFGMECH_PCIE)
+ device_printf(dev, "Enabled ECAM PCIe accesses\n");
+}
+
static int
legacy_attach(device_t dev)
{
device_t child;
+
+ legacy_pci_cfgregopen(dev);
/*
* Let our child drivers identify any child devices that they
_______________________________________________
[email protected] mailing list
https://lists.freebsd.org/mailman/listinfo/svn-src-all
To unsubscribe, send any mail to "[email protected]"
