Author: alc
Date: Sun Sep 15 21:27:14 2019
New Revision: 352367
URL: https://svnweb.freebsd.org/changeset/base/352367
Log:
MFC r349905
According to Section D5.10.3 "Maintenance requirements on changing System
register values" of the architecture manual, an isb instruction should be
executed after updating ttbr0_el1 and before invalidating the TLB.
Modified:
stable/12/sys/arm64/arm64/efirt_machdep.c
stable/12/sys/arm64/arm64/pmap.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/arm64/efirt_machdep.c
==============================================================================
--- stable/12/sys/arm64/arm64/efirt_machdep.c Sun Sep 15 21:13:13 2019
(r352366)
+++ stable/12/sys/arm64/arm64/efirt_machdep.c Sun Sep 15 21:27:14 2019
(r352367)
@@ -245,6 +245,7 @@ efi_arch_enter(void)
__asm __volatile(
"msr ttbr0_el1, %0 \n"
+ "isb \n"
"dsb ishst \n"
"tlbi vmalle1is \n"
"dsb ish \n"
@@ -262,6 +263,7 @@ efi_arch_leave(void)
td = curthread;
__asm __volatile(
"msr ttbr0_el1, %0 \n"
+ "isb \n"
"dsb ishst \n"
"tlbi vmalle1is \n"
"dsb ish \n"
Modified: stable/12/sys/arm64/arm64/pmap.c
==============================================================================
--- stable/12/sys/arm64/arm64/pmap.c Sun Sep 15 21:13:13 2019
(r352366)
+++ stable/12/sys/arm64/arm64/pmap.c Sun Sep 15 21:27:14 2019
(r352367)
@@ -5175,8 +5175,10 @@ pmap_activate(struct thread *td)
critical_enter();
pmap = vmspace_pmap(td->td_proc->p_vmspace);
td->td_proc->p_md.md_l0addr = vtophys(pmap->pm_l0);
- __asm __volatile("msr ttbr0_el1, %0" : :
- "r"(td->td_proc->p_md.md_l0addr));
+ __asm __volatile(
+ "msr ttbr0_el1, %0 \n"
+ "isb \n"
+ : : "r"(td->td_proc->p_md.md_l0addr));
pmap_invalidate_all(pmap);
critical_exit();
}
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