Author: jhibbits
Date: Fri Nov 8 03:45:13 2019
New Revision: 354526
URL: https://svnweb.freebsd.org/changeset/base/354526
Log:
powerpc/booke: Make the TLB save area and mask match
Since TLB_MAXNEST is 3, the insert mask should only be 2 bits. Given that 2
bits counts to 4, and that we already have plenty of space wasted in
padding, make the nest level 4 to match the mask.
Modified:
head/sys/powerpc/booke/trap_subr.S
head/sys/powerpc/include/pcpu.h
Modified: head/sys/powerpc/booke/trap_subr.S
==============================================================================
--- head/sys/powerpc/booke/trap_subr.S Fri Nov 8 03:36:19 2019
(r354525)
+++ head/sys/powerpc/booke/trap_subr.S Fri Nov 8 03:45:13 2019
(r354526)
@@ -365,14 +365,14 @@
ld %r30, (TLBSAVE_BOOKE_R30)(br); \
ld %r31, (TLBSAVE_BOOKE_R31)(br);
#define TLB_NEST(outr,inr) \
- rlwinm outr, inr, 7, 22, 24; /* 8 x TLBSAVE_LEN */
+ rlwinm outr, inr, 7, 23, 24; /* 8 x TLBSAVE_LEN */
#else
#define TLB_SAVE_REGS(br) \
stmw %r20, TLBSAVE_BOOKE_R20(br)
#define TLB_RESTORE_REGS(br) \
lmw %r20, TLBSAVE_BOOKE_R20(br)
#define TLB_NEST(outr,inr) \
- rlwinm outr, inr, 6, 23, 25; /* 4 x TLBSAVE_LEN */
+ rlwinm outr, inr, 6, 24, 25; /* 4 x TLBSAVE_LEN */
#endif
#define TLB_PROLOG \
mtspr SPR_SPRG4, %r1; /* Save SP */ \
Modified: head/sys/powerpc/include/pcpu.h
==============================================================================
--- head/sys/powerpc/include/pcpu.h Fri Nov 8 03:36:19 2019
(r354525)
+++ head/sys/powerpc/include/pcpu.h Fri Nov 8 03:45:13 2019
(r354526)
@@ -77,14 +77,14 @@ struct pvo_entry;
#endif
#define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2)
-#define BOOKE_TLB_MAXNEST 3
+#define BOOKE_TLB_MAXNEST 4
#define BOOKE_TLB_SAVELEN 16
#define BOOKE_TLBSAVE_LEN (BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST)
#ifdef __powerpc64__
#define BOOKE_PCPU_PAD 901
#else
-#define BOOKE_PCPU_PAD 429
+#define BOOKE_PCPU_PAD 365
#endif
#define PCPU_MD_BOOKE_FIELDS \
register_t critsave[BOOKE_CRITSAVE_LEN]; \
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