Author: manu
Date: Thu Nov 28 17:42:11 2019
New Revision: 355176
URL: https://svnweb.freebsd.org/changeset/base/355176
Log:
MFC r347097, r351187, r351551-r351552, r352849-r352852
r347097 by ganbold:
Add emmc clock definitions for Rockchip RK3399 SoC.
r351187 by mmel:
Improve rk_pinctrl driver:
- add support for 'output-low', 'output-high', 'output-low' and
'output-enable' properties. These are use in RK3288 DT files
- add support for RK3288
- to reduce overall file size, use local macros for initialization
of pinctrl description structures.
r351551:
arm64: rk3328: pinctrl: Add gpio banks and fix iomux
Since r351187 the pinctrl driver need to know the gpio bank as it
directly attach the gpio driver to handle some setup that might
be present in the dts, add the gpio banks table for rk3328.
While here fix some IOMUX definition that prevented to boot
on RK3328 as pinctrl wasn't configured correctly.
Submitted by: mmel (original version)
MFC With: r351187
r351552:
arm64: rk3399: pinctrl: Add gpio banks and fix iomux
Since r351187 the pinctrl driver need to know the gpio bank as it
directly attach the gpio driver to handle some setup that might
be present in the dts, add the gpio banks table for rk3399.
While here fix some IOMUX definition that prevented to boot
on RK3399 as pinctrl wasn't configured correctly.
Submitted by: mmel (original version)
MFC With: r351187
r352849:
arm64: rockchip: rk3399: Add usb2 clocks
r352850:
arm64: rockchip: Implement resets
Module resets where not implemented when rockchip clocks were commited.
Implement them.
Since all resets registers are contiguous a driver only need to give
the start offset and the number of resets. This avoid to have to declare
every resets.
r352851:
arm64: rockchip: Fix map_gpio
The map_gpio function wasn't correct, the first element is the pin
and not the phandle.
r352852:
dwc: Add more delay for chip reset
On rockchip board it seems that the value in the DTS
are not enough for reseting the chip, I don't know if
the value are really incorrect or if DELAY is not precise
enough or if the rockchip gpio driver have some "lag" of some
kind or not.
For now just add more delay.
Modified:
stable/12/sys/arm64/rockchip/clk/rk3328_cru.c
stable/12/sys/arm64/rockchip/clk/rk3399_cru.c
stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c
stable/12/sys/arm64/rockchip/clk/rk_cru.c
stable/12/sys/arm64/rockchip/clk/rk_cru.h
stable/12/sys/arm64/rockchip/rk_gpio.c
stable/12/sys/arm64/rockchip/rk_pinctrl.c
stable/12/sys/dev/dwc/if_dwc.c
Directory Properties:
stable/12/ (props changed)
Modified: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c
==============================================================================
--- stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Thu Nov 28 17:34:49
2019 (r355175)
+++ stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Thu Nov 28 17:42:11
2019 (r355176)
@@ -1083,6 +1083,9 @@ rk3328_cru_attach(device_t dev)
sc->clks = rk3328_clks;
sc->nclks = nitems(rk3328_clks);
+ sc->reset_offset = 0x300;
+ sc->reset_num = 184;
+
return (rk_cru_attach(dev));
}
Modified: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c
==============================================================================
--- stable/12/sys/arm64/rockchip/clk/rk3399_cru.c Thu Nov 28 17:34:49
2019 (r355175)
+++ stable/12/sys/arm64/rockchip/clk/rk3399_cru.c Thu Nov 28 17:42:11
2019 (r355176)
@@ -52,6 +52,11 @@ __FBSDID("$FreeBSD$");
/* GATES */
+#define SCLK_USB2PHY0_REF 123
+#define SCLK_USB2PHY1_REF 124
+#define ACLK_EMMC_CORE 241
+#define ACLK_EMMC_NOC 242
+#define ACLK_EMMC_GRF 243
#define PCLK_GPIO2 336
#define PCLK_GPIO3 337
#define PCLK_GPIO4 338
@@ -61,6 +66,10 @@ __FBSDID("$FreeBSD$");
#define PCLK_I2C5 344
#define PCLK_I2C6 345
#define PCLK_I2C7 346
+#define HCLK_HOST0 456
+#define HCLK_HOST0_ARB 457
+#define HCLK_HOST1 458
+#define HCLK_HOST1_ARB 459
#define HCLK_SDMMC 462
static struct rk_cru_gate rk3399_gates[] = {
@@ -80,6 +89,12 @@ static struct rk_cru_gate rk3399_gates[] = {
CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0)
CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1)
+ /* CRU_CLKGATE_CON6 */
+ CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12)
+ CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13)
+ CRU_GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 0x318, 5)
+ CRU_GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 0x318, 6)
+
/* CRU_CLKGATE_CON7 */
CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0)
CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1)
@@ -88,6 +103,12 @@ static struct rk_cru_gate rk3399_gates[] = {
CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
+ /* CRU_CLKGATE_CON20 */
+ CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5)
+ CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6)
+ CRU_GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0x350, 7)
+ CRU_GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0x350, 8)
+
/* CRU_CLKGATE_CON22 */
CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5)
CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6)
@@ -101,6 +122,11 @@ static struct rk_cru_gate rk3399_gates[] = {
CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5)
+ /* CRU_CLKGATE_CON32 */
+ CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8)
+ CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9)
+ CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10)
+
/* CRU_CLKGATE_CON33 */
CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8)
};
@@ -1445,6 +1471,60 @@ static struct rk_clk_composite_def sclk_sdmmc = {
.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
};
+/*
+ * emmc
+ */
+
+#define SCLK_EMMC 78
+
+static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"};
+
+static struct rk_clk_composite_def sclk_emmc = {
+ .clkdef = {
+ .id = SCLK_EMMC,
+ .name = "sclk_emmc",
+ .parent_names = sclk_emmc_parents,
+ .parent_cnt = nitems(sclk_emmc_parents),
+ },
+
+ .muxdiv_offset = 0x158,
+ .mux_shift = 8,
+ .mux_width = 3,
+
+ .div_shift = 0,
+ .div_width = 7,
+
+ .gate_offset = 0x318,
+ .gate_shift = 14,
+
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
+};
+
+#define ACLK_EMMC 240
+
+static const char *aclk_emmc_parents[] = {
+ "cpll_aclk_emmc_src",
+ "gpll_aclk_emmc_src"
+};
+
+static struct rk_clk_composite_def aclk_emmc = {
+ .clkdef = {
+ .id = ACLK_EMMC,
+ .name = "aclk_emmc",
+ .parent_names = aclk_emmc_parents,
+ .parent_cnt = nitems(aclk_emmc_parents),
+ },
+
+ .muxdiv_offset = 0x154,
+ .mux_shift = 7,
+ .mux_width = 1,
+
+ .div_shift = 0,
+ .div_width = 5,
+
+ .flags = RK_CLK_COMPOSITE_HAVE_MUX,
+};
+
static struct rk_clk rk3399_clks[] = {
{
.type = RK3399_CLK_PLL,
@@ -1553,6 +1633,15 @@ static struct rk_clk rk3399_clks[] = {
.type = RK_CLK_COMPOSITE,
.clk.composite = &sclk_sdmmc,
},
+
+ {
+ .type = RK_CLK_COMPOSITE,
+ .clk.composite = &sclk_emmc,
+ },
+ {
+ .type = RK_CLK_COMPOSITE,
+ .clk.composite = &aclk_emmc,
+ },
};
static int
@@ -1583,6 +1672,9 @@ rk3399_cru_attach(device_t dev)
sc->clks = rk3399_clks;
sc->nclks = nitems(rk3399_clks);
+
+ sc->reset_offset = 0x400;
+ sc->reset_num = 335;
return (rk_cru_attach(dev));
}
Modified: stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c
==============================================================================
--- stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c Thu Nov 28 17:34:49
2019 (r355175)
+++ stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c Thu Nov 28 17:42:11
2019 (r355176)
@@ -846,6 +846,9 @@ rk3399_pmucru_attach(device_t dev)
sc->clks = rk3399_pmu_clks;
sc->nclks = nitems(rk3399_pmu_clks);
+ sc->reset_offset = 0x110;
+ sc->reset_num = 30;
+
return (rk_cru_attach(dev));
}
Modified: stable/12/sys/arm64/rockchip/clk/rk_cru.c
==============================================================================
--- stable/12/sys/arm64/rockchip/clk/rk_cru.c Thu Nov 28 17:34:49 2019
(r355175)
+++ stable/12/sys/arm64/rockchip/clk/rk_cru.c Thu Nov 28 17:42:11 2019
(r355176)
@@ -112,20 +112,23 @@ static int
rk_cru_reset_assert(device_t dev, intptr_t id, bool reset)
{
struct rk_cru_softc *sc;
+ uint32_t reg;
+ int bit;
uint32_t val;
sc = device_get_softc(dev);
- if (id >= sc->nresets || sc->resets[id].offset == 0)
- return (0);
+ if (id > sc->reset_num)
+ return (ENXIO);
+ reg = sc->reset_offset + id / 16 * 4;
+ bit = id % 16;
+
mtx_lock(&sc->mtx);
- val = CCU_READ4(sc, sc->resets[id].offset);
+ val = 0;
if (reset)
- val &= ~(1 << sc->resets[id].shift);
- else
- val |= 1 << sc->resets[id].shift;
- CCU_WRITE4(sc, sc->resets[id].offset, val);
+ val = (1 << bit);
+ CCU_WRITE4(sc, reg, val | ((1 << bit) << 16));
mtx_unlock(&sc->mtx);
return (0);
@@ -135,18 +138,25 @@ static int
rk_cru_reset_is_asserted(device_t dev, intptr_t id, bool *reset)
{
struct rk_cru_softc *sc;
+ uint32_t reg;
+ int bit;
uint32_t val;
sc = device_get_softc(dev);
- if (id >= sc->nresets || sc->resets[id].offset == 0)
- return (0);
+ if (id > sc->reset_num)
+ return (ENXIO);
+ reg = sc->reset_offset + id / 16 * 4;
+ bit = id % 16;
mtx_lock(&sc->mtx);
- val = CCU_READ4(sc, sc->resets[id].offset);
- *reset = (val & (1 << sc->resets[id].shift)) != 0 ? false : true;
+ val = CCU_READ4(sc, reg);
mtx_unlock(&sc->mtx);
+ *reset = true;
+ if (val & (1 << bit))
+ *reset = true;
+
return (0);
}
@@ -254,8 +264,8 @@ rk_cru_attach(device_t dev)
clk_set_assigned(dev, node);
/* If we have resets, register our self as a reset provider */
- if (sc->resets)
- hwreset_register_ofw_provider(dev);
+ /* if (sc->resets) */
+ /* hwreset_register_ofw_provider(dev); */
return (0);
}
Modified: stable/12/sys/arm64/rockchip/clk/rk_cru.h
==============================================================================
--- stable/12/sys/arm64/rockchip/clk/rk_cru.h Thu Nov 28 17:34:49 2019
(r355175)
+++ stable/12/sys/arm64/rockchip/clk/rk_cru.h Thu Nov 28 17:42:11 2019
(r355176)
@@ -37,11 +37,6 @@
#include <arm64/rockchip/clk/rk_clk_mux.h>
#include <arm64/rockchip/clk/rk_clk_pll.h>
-struct rk_cru_reset {
- uint32_t offset;
- uint32_t shift;
-};
-
struct rk_cru_gate {
const char *name;
const char *parent_name;
@@ -84,8 +79,8 @@ struct rk_cru_softc {
struct clkdom *clkdom;
struct mtx mtx;
int type;
- struct rk_cru_reset *resets;
- int nresets;
+ uint32_t reset_offset;
+ uint32_t reset_num;
struct rk_cru_gate *gates;
int ngates;
struct rk_clk *clks;
Modified: stable/12/sys/arm64/rockchip/rk_gpio.c
==============================================================================
--- stable/12/sys/arm64/rockchip/rk_gpio.c Thu Nov 28 17:34:49 2019
(r355175)
+++ stable/12/sys/arm64/rockchip/rk_gpio.c Thu Nov 28 17:42:11 2019
(r355176)
@@ -388,9 +388,9 @@ rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle
pcell_t *gpios, uint32_t *pin, uint32_t *flags)
{
- /* The gpios are mapped as <gpio-phandle pin flags> */
- *pin = gpios[1];
- *flags = gpios[2];
+ /* The gpios are mapped as <pin flags> */
+ *pin = gpios[0];
+ *flags = gpios[1];
return (0);
}
Modified: stable/12/sys/arm64/rockchip/rk_pinctrl.c
==============================================================================
--- stable/12/sys/arm64/rockchip/rk_pinctrl.c Thu Nov 28 17:34:49 2019
(r355175)
+++ stable/12/sys/arm64/rockchip/rk_pinctrl.c Thu Nov 28 17:42:11 2019
(r355176)
@@ -34,11 +34,12 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/bus.h>
+#include <sys/gpio.h>
#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/rman.h>
#include <sys/lock.h>
+#include <sys/module.h>
#include <sys/mutex.h>
+#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/resource.h>
@@ -53,10 +54,9 @@ __FBSDID("$FreeBSD$");
#include <dev/extres/syscon/syscon.h>
+#include "gpio_if.h"
#include "syscon_if.h"
-#include "opt_soc.h"
-
struct rk_pinctrl_pin_drive {
uint32_t bank;
uint32_t subbank;
@@ -66,8 +66,8 @@ struct rk_pinctrl_pin_drive {
};
struct rk_pinctrl_bank {
- uint32_t bank_num;
- uint32_t subbank_num;
+ uint32_t bank;
+ uint32_t subbank;
uint32_t offset;
uint32_t nbits;
};
@@ -81,6 +81,13 @@ struct rk_pinctrl_pin_fixup {
uint32_t mask;
};
+struct rk_pinctrl_gpio {
+ uint32_t bank;
+ char *gpio_name;
+ device_t gpio_dev;
+};
+
+
struct rk_pinctrl_softc;
struct rk_pinctrl_conf {
@@ -90,8 +97,10 @@ struct rk_pinctrl_conf {
uint32_t npin_fixup;
struct rk_pinctrl_pin_drive *pin_drive;
uint32_t npin_drive;
- uint32_t (*get_pd_offset)(struct
rk_pinctrl_softc *, uint32_t);
- struct syscon *(*get_syscon)(struct rk_pinctrl_softc
*, uint32_t);
+ struct rk_pinctrl_gpio *gpio_bank;
+ uint32_t ngpio_bank;
+ uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t);
+ struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t);
};
struct rk_pinctrl_softc {
@@ -102,218 +111,395 @@ struct rk_pinctrl_softc {
struct rk_pinctrl_conf *conf;
};
+#define RK_IOMUX(_bank, _subbank, _offset, _nbits)
\
+{ \
+ .bank = _bank, \
+ .subbank = _subbank, \
+ .offset = _offset, \
+ .nbits = _nbits, \
+}
+
+#define RK_PINFIX(_bank, _pin, _reg, _bit, _mask)
\
+{ \
+ .bank = _bank, \
+ .pin = _pin, \
+ .reg = _reg, \
+ .bit = _bit, \
+ .mask = _mask, \
+}
+
+#define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma)
\
+{ \
+ .bank = _bank, \
+ .subbank = _subbank, \
+ .offset = _offset, \
+ .value = _value, \
+ .ma = _ma, \
+}
+#define RK_GPIO(_bank, _name)
\
+{ \
+ .bank = _bank, \
+ .gpio_name = _name, \
+}
+
+static struct rk_pinctrl_gpio rk3288_gpio_bank[] = {
+ RK_GPIO(0, "gpio0"),
+ RK_GPIO(1, "gpio1"),
+ RK_GPIO(2, "gpio2"),
+ RK_GPIO(3, "gpio3"),
+ RK_GPIO(4, "gpio4"),
+ RK_GPIO(5, "gpio5"),
+ RK_GPIO(6, "gpio6"),
+ RK_GPIO(7, "gpio7"),
+ RK_GPIO(8, "gpio8"),
+};
+
+static struct rk_pinctrl_bank rk3288_iomux_bank[] = {
+ /* bank sub offs nbits */
+ /* PMU */
+ RK_IOMUX(0, 0, 0x0084, 2),
+ RK_IOMUX(0, 1, 0x0088, 2),
+ RK_IOMUX(0, 2, 0x008C, 2),
+ /* GFR */
+ RK_IOMUX(1, 3, 0x000C, 2),
+ RK_IOMUX(2, 0, 0x0010, 2),
+ RK_IOMUX(2, 1, 0x0014, 2),
+ RK_IOMUX(2, 2, 0x0018, 2),
+ RK_IOMUX(2, 3, 0x001C, 2),
+ RK_IOMUX(3, 0, 0x0020, 2),
+ RK_IOMUX(3, 1, 0x0024, 2),
+ RK_IOMUX(3, 2, 0x0028, 2),
+ RK_IOMUX(3, 3, 0x002C, 4),
+ RK_IOMUX(4, 0, 0x0034, 4),
+ RK_IOMUX(4, 1, 0x003C, 4),
+ RK_IOMUX(4, 2, 0x0044, 2),
+ RK_IOMUX(4, 3, 0x0048, 2),
+ /* 5,0 - Empty */
+ RK_IOMUX(5, 1, 0x0050, 2),
+ RK_IOMUX(5, 2, 0x0054, 2),
+ /* 5,3 - Empty */
+ RK_IOMUX(6, 0, 0x005C, 2),
+ RK_IOMUX(6, 1, 0x0060, 2),
+ RK_IOMUX(6, 2, 0x0064, 2),
+ /* 6,3 - Empty */
+ RK_IOMUX(7, 0, 0x006C, 2),
+ RK_IOMUX(7, 1, 0x0070, 2),
+ RK_IOMUX(7, 2, 0x0074, 4),
+ /* 7,3 - Empty */
+ RK_IOMUX(8, 0, 0x0080, 2),
+ RK_IOMUX(8, 1, 0x0084, 2),
+ /* 8,2 - Empty */
+ /* 8,3 - Empty */
+
+};
+
+static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = {
+};
+
+static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = {
+ /* bank sub offs val ma */
+ /* GPIO0A (PMU)*/
+ RK_PINDRIVE(0, 0, 0x070, 0, 2),
+ RK_PINDRIVE(0, 0, 0x070, 1, 4),
+ RK_PINDRIVE(0, 0, 0x070, 2, 8),
+ RK_PINDRIVE(0, 0, 0x070, 3, 12),
+
+ /* GPIO0B (PMU)*/
+ RK_PINDRIVE(0, 1, 0x074, 0, 2),
+ RK_PINDRIVE(0, 1, 0x074, 1, 4),
+ RK_PINDRIVE(0, 1, 0x074, 2, 8),
+ RK_PINDRIVE(0, 1, 0x074, 3, 12),
+
+ /* GPIO0C (PMU)*/
+ RK_PINDRIVE(0, 2, 0x078, 0, 2),
+ RK_PINDRIVE(0, 2, 0x078, 1, 4),
+ RK_PINDRIVE(0, 2, 0x078, 2, 8),
+ RK_PINDRIVE(0, 2, 0x078, 3, 12),
+
+ /* GPIO1D */
+ RK_PINDRIVE(1, 3, 0x1CC, 0, 2),
+ RK_PINDRIVE(1, 3, 0x1CC, 1, 4),
+ RK_PINDRIVE(1, 3, 0x1CC, 2, 8),
+ RK_PINDRIVE(1, 3, 0x1CC, 3, 12),
+
+ /* GPIO2A */
+ RK_PINDRIVE(2, 0, 0x1D0, 0, 2),
+ RK_PINDRIVE(2, 0, 0x1D0, 1, 4),
+ RK_PINDRIVE(2, 0, 0x1D0, 2, 8),
+ RK_PINDRIVE(2, 0, 0x1D0, 3, 12),
+
+ /* GPIO2B */
+ RK_PINDRIVE(2, 1, 0x1D4, 0, 2),
+ RK_PINDRIVE(2, 1, 0x1D4, 1, 4),
+ RK_PINDRIVE(2, 1, 0x1D4, 2, 8),
+ RK_PINDRIVE(2, 1, 0x1D4, 3, 12),
+
+ /* GPIO2C */
+ RK_PINDRIVE(2, 2, 0x1D8, 0, 2),
+ RK_PINDRIVE(2, 2, 0x1D8, 1, 4),
+ RK_PINDRIVE(2, 2, 0x1D8, 2, 8),
+ RK_PINDRIVE(2, 2, 0x1D8, 3, 12),
+
+ /* GPIO2D */
+ RK_PINDRIVE(2, 3, 0x1DC, 0, 2),
+ RK_PINDRIVE(2, 3, 0x1DC, 1, 4),
+ RK_PINDRIVE(2, 3, 0x1DC, 2, 8),
+ RK_PINDRIVE(2, 3, 0x1DC, 3, 12),
+
+ /* GPIO3A */
+ RK_PINDRIVE(3, 0, 0x1E0, 0, 2),
+ RK_PINDRIVE(3, 0, 0x1E0, 1, 4),
+ RK_PINDRIVE(3, 0, 0x1E0, 2, 8),
+ RK_PINDRIVE(3, 0, 0x1E0, 3, 12),
+
+ /* GPIO3B */
+ RK_PINDRIVE(3, 1, 0x1E4, 0, 2),
+ RK_PINDRIVE(3, 1, 0x1E4, 1, 4),
+ RK_PINDRIVE(3, 1, 0x1E4, 2, 8),
+ RK_PINDRIVE(3, 1, 0x1E4, 3, 12),
+
+ /* GPIO3C */
+ RK_PINDRIVE(3, 2, 0x1E8, 0, 2),
+ RK_PINDRIVE(3, 2, 0x1E8, 1, 4),
+ RK_PINDRIVE(3, 2, 0x1E8, 2, 8),
+ RK_PINDRIVE(3, 2, 0x1E8, 3, 12),
+
+ /* GPIO3D */
+ RK_PINDRIVE(3, 3, 0x1EC, 0, 2),
+ RK_PINDRIVE(3, 3, 0x1EC, 1, 4),
+ RK_PINDRIVE(3, 3, 0x1EC, 2, 8),
+ RK_PINDRIVE(3, 3, 0x1EC, 3, 12),
+
+ /* GPIO4A */
+ RK_PINDRIVE(4, 0, 0x1F0, 0, 2),
+ RK_PINDRIVE(4, 0, 0x1F0, 1, 4),
+ RK_PINDRIVE(4, 0, 0x1F0, 2, 8),
+ RK_PINDRIVE(4, 0, 0x1F0, 3, 12),
+
+ /* GPIO4B */
+ RK_PINDRIVE(4, 1, 0x1F4, 0, 2),
+ RK_PINDRIVE(4, 1, 0x1F4, 1, 4),
+ RK_PINDRIVE(4, 1, 0x1F4, 2, 8),
+ RK_PINDRIVE(4, 1, 0x1F4, 3, 12),
+
+ /* GPIO4C */
+ RK_PINDRIVE(4, 2, 0x1F8, 0, 2),
+ RK_PINDRIVE(4, 2, 0x1F8, 1, 4),
+ RK_PINDRIVE(4, 2, 0x1F8, 2, 8),
+ RK_PINDRIVE(4, 2, 0x1F8, 3, 12),
+
+ /* GPIO4D */
+ RK_PINDRIVE(4, 3, 0x1FC, 0, 2),
+ RK_PINDRIVE(4, 3, 0x1FC, 1, 4),
+ RK_PINDRIVE(4, 3, 0x1FC, 2, 8),
+ RK_PINDRIVE(4, 3, 0x1FC, 3, 12),
+
+ /* GPIO5B */
+ RK_PINDRIVE(5, 1, 0x204, 0, 2),
+ RK_PINDRIVE(5, 1, 0x204, 1, 4),
+ RK_PINDRIVE(5, 1, 0x204, 2, 8),
+ RK_PINDRIVE(5, 1, 0x204, 3, 12),
+
+ /* GPIO5C */
+ RK_PINDRIVE(5, 2, 0x208, 0, 2),
+ RK_PINDRIVE(5, 2, 0x208, 1, 4),
+ RK_PINDRIVE(5, 2, 0x208, 2, 8),
+ RK_PINDRIVE(5, 2, 0x208, 3, 12),
+
+ /* GPIO6A */
+ RK_PINDRIVE(6, 0, 0x210, 0, 2),
+ RK_PINDRIVE(6, 0, 0x210, 1, 4),
+ RK_PINDRIVE(6, 0, 0x210, 2, 8),
+ RK_PINDRIVE(6, 0, 0x210, 3, 12),
+
+ /* GPIO6B */
+ RK_PINDRIVE(6, 1, 0x214, 0, 2),
+ RK_PINDRIVE(6, 1, 0x214, 1, 4),
+ RK_PINDRIVE(6, 1, 0x214, 2, 8),
+ RK_PINDRIVE(6, 1, 0x214, 3, 12),
+
+ /* GPIO6C */
+ RK_PINDRIVE(6, 2, 0x218, 0, 2),
+ RK_PINDRIVE(6, 2, 0x218, 1, 4),
+ RK_PINDRIVE(6, 2, 0x218, 2, 8),
+ RK_PINDRIVE(6, 2, 0x218, 3, 12),
+
+ /* GPIO7A */
+ RK_PINDRIVE(7, 0, 0x220, 0, 2),
+ RK_PINDRIVE(7, 0, 0x220, 1, 4),
+ RK_PINDRIVE(7, 0, 0x220, 2, 8),
+ RK_PINDRIVE(7, 0, 0x220, 3, 12),
+
+ /* GPIO7B */
+ RK_PINDRIVE(7, 1, 0x224, 0, 2),
+ RK_PINDRIVE(7, 1, 0x224, 1, 4),
+ RK_PINDRIVE(7, 1, 0x224, 2, 8),
+ RK_PINDRIVE(7, 1, 0x224, 3, 12),
+
+ /* GPIO7C */
+ RK_PINDRIVE(7, 2, 0x228, 0, 2),
+ RK_PINDRIVE(7, 2, 0x228, 1, 4),
+ RK_PINDRIVE(7, 2, 0x228, 2, 8),
+ RK_PINDRIVE(7, 2, 0x228, 3, 12),
+
+ /* GPIO8A */
+ RK_PINDRIVE(8, 0, 0x230, 0, 2),
+ RK_PINDRIVE(8, 0, 0x230, 1, 4),
+ RK_PINDRIVE(8, 0, 0x230, 2, 8),
+ RK_PINDRIVE(8, 0, 0x230, 3, 12),
+
+ /* GPIO8B */
+ RK_PINDRIVE(8, 1, 0x234, 0, 2),
+ RK_PINDRIVE(8, 1, 0x234, 1, 4),
+ RK_PINDRIVE(8, 1, 0x234, 2, 8),
+ RK_PINDRIVE(8, 1, 0x234, 3, 12),
+};
+
+static uint32_t
+rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
+{
+ if (bank == 0)
+ return (0x064); /* PMU */
+ return (0x130);
+}
+
+static struct syscon *
+rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
+{
+ if (bank == 0)
+ return (sc->pmu);
+ return (sc->grf);
+}
+
+struct rk_pinctrl_conf rk3288_conf = {
+ .iomux_conf = rk3288_iomux_bank,
+ .iomux_nbanks = nitems(rk3288_iomux_bank),
+ .pin_fixup = rk3288_pin_fixup,
+ .npin_fixup = nitems(rk3288_pin_fixup),
+ .pin_drive = rk3288_pin_drive,
+ .npin_drive = nitems(rk3288_pin_drive),
+ .gpio_bank = rk3288_gpio_bank,
+ .ngpio_bank = nitems(rk3288_gpio_bank),
+ .get_pd_offset = rk3288_get_pd_offset,
+ .get_syscon = rk3288_get_syscon,
+};
+
+static struct rk_pinctrl_gpio rk3328_gpio_bank[] = {
+ RK_GPIO(0, "gpio0"),
+ RK_GPIO(1, "gpio1"),
+ RK_GPIO(2, "gpio2"),
+ RK_GPIO(3, "gpio3"),
+};
+
static struct rk_pinctrl_bank rk3328_iomux_bank[] = {
- {
- .bank_num = 0,
- .subbank_num = 0,
- .offset = 0x00,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 1,
- .offset = 0x04,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 2,
- .offset = 0x08,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 3,
- .offset = 0xc,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 0,
- .offset = 0x10,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 1,
- .offset = 0x14,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 2,
- .offset = 0x18,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 3,
- .offset = 0x1C,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 0,
- .offset = 0x20,
- .nbits = 2,
- },
- {
- .bank_num = 2,
- .subbank_num = 1,
- .offset = 0x24,
- .nbits = 3,
- },
- {
- .bank_num = 2,
- .subbank_num = 2,
- .offset = 0x2c,
- .nbits = 3,
- },
- {
- .bank_num = 2,
- .subbank_num = 3,
- .offset = 0x34,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 0,
- .offset = 0x38,
- .nbits = 3,
- },
- {
- .bank_num = 3,
- .subbank_num = 1,
- .offset = 0x40,
- .nbits = 3,
- },
- {
- .bank_num = 3,
- .subbank_num = 2,
- .offset = 0x48,
- .nbits = 2,
- },
- {
- .bank_num = 3,
- .subbank_num = 3,
- .offset = 0x4c,
- .nbits = 2,
- },
+ /* bank sub offs nbits */
+ RK_IOMUX(0, 0, 0x0000, 2),
+ RK_IOMUX(0, 1, 0x0004, 2),
+ RK_IOMUX(0, 2, 0x0008, 2),
+ RK_IOMUX(0, 3, 0x000C, 2),
+ RK_IOMUX(1, 0, 0x0010, 2),
+ RK_IOMUX(1, 1, 0x0014, 2),
+ RK_IOMUX(1, 2, 0x0018, 2),
+ RK_IOMUX(1, 3, 0x001C, 2),
+ RK_IOMUX(2, 0, 0x0020, 2),
+ RK_IOMUX(2, 1, 0x0024, 3),
+ RK_IOMUX(2, 2, 0x002c, 3),
+ RK_IOMUX(2, 3, 0x0034, 2),
+ RK_IOMUX(3, 0, 0x0038, 3),
+ RK_IOMUX(3, 1, 0x0040, 3),
+ RK_IOMUX(3, 2, 0x0048, 2),
+ RK_IOMUX(3, 3, 0x004c, 2),
};
static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = {
- {
- .bank = 2,
- .pin = 12,
- .reg = 0x24,
- .bit = 8,
- .mask = 0x300,
- },
- {
- .bank = 2,
- .pin = 15,
- .reg = 0x28,
- .bit = 0,
- .mask = 0x7,
- },
- {
- .bank = 2,
- .pin = 23,
- .reg = 0x30,
- .bit = 14,
- .mask = 0x6000,
- },
+ /* bank pin reg bit mask */
+ RK_PINFIX(2, 12, 0x24, 8, 0x300),
+ RK_PINFIX(2, 15, 0x28, 0, 0x7),
+ RK_PINFIX(2, 23, 0x30, 14, 0x6000),
};
-#define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \
- { \
- .bank = _bank, \
- .subbank = _subbank, \
- .offset = _offset, \
- .value = _value, \
- .ma = _ma, \
- },
static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = {
- RK_PINDRIVE(0, 0, 0x200, 0, 2)
- RK_PINDRIVE(0, 0, 0x200, 1, 4)
- RK_PINDRIVE(0, 0, 0x200, 2, 8)
- RK_PINDRIVE(0, 0, 0x200, 3, 12)
+ /* bank sub offs val ma */
+ RK_PINDRIVE(0, 0, 0x200, 0, 2),
+ RK_PINDRIVE(0, 0, 0x200, 1, 4),
+ RK_PINDRIVE(0, 0, 0x200, 2, 8),
+ RK_PINDRIVE(0, 0, 0x200, 3, 12),
- RK_PINDRIVE(0, 1, 0x204, 0, 2)
- RK_PINDRIVE(0, 1, 0x204, 1, 4)
- RK_PINDRIVE(0, 1, 0x204, 2, 8)
- RK_PINDRIVE(0, 1, 0x204, 3, 12)
+ RK_PINDRIVE(0, 1, 0x204, 0, 2),
+ RK_PINDRIVE(0, 1, 0x204, 1, 4),
+ RK_PINDRIVE(0, 1, 0x204, 2, 8),
+ RK_PINDRIVE(0, 1, 0x204, 3, 12),
- RK_PINDRIVE(0, 2, 0x208, 0, 2)
- RK_PINDRIVE(0, 2, 0x208, 1, 4)
- RK_PINDRIVE(0, 2, 0x208, 2, 8)
- RK_PINDRIVE(0, 2, 0x208, 3, 12)
+ RK_PINDRIVE(0, 2, 0x208, 0, 2),
+ RK_PINDRIVE(0, 2, 0x208, 1, 4),
+ RK_PINDRIVE(0, 2, 0x208, 2, 8),
+ RK_PINDRIVE(0, 2, 0x208, 3, 12),
- RK_PINDRIVE(0, 3, 0x20C, 0, 2)
- RK_PINDRIVE(0, 3, 0x20C, 1, 4)
- RK_PINDRIVE(0, 3, 0x20C, 2, 8)
- RK_PINDRIVE(0, 3, 0x20C, 3, 12)
+ RK_PINDRIVE(0, 3, 0x20C, 0, 2),
+ RK_PINDRIVE(0, 3, 0x20C, 1, 4),
+ RK_PINDRIVE(0, 3, 0x20C, 2, 8),
+ RK_PINDRIVE(0, 3, 0x20C, 3, 12),
- RK_PINDRIVE(1, 0, 0x210, 0, 2)
- RK_PINDRIVE(1, 0, 0x210, 1, 4)
- RK_PINDRIVE(1, 0, 0x210, 2, 8)
- RK_PINDRIVE(1, 0, 0x210, 3, 12)
+ RK_PINDRIVE(1, 0, 0x210, 0, 2),
+ RK_PINDRIVE(1, 0, 0x210, 1, 4),
+ RK_PINDRIVE(1, 0, 0x210, 2, 8),
+ RK_PINDRIVE(1, 0, 0x210, 3, 12),
- RK_PINDRIVE(1, 1, 0x214, 0, 2)
- RK_PINDRIVE(1, 1, 0x214, 1, 4)
- RK_PINDRIVE(1, 1, 0x214, 2, 8)
- RK_PINDRIVE(1, 1, 0x214, 3, 12)
+ RK_PINDRIVE(1, 1, 0x214, 0, 2),
+ RK_PINDRIVE(1, 1, 0x214, 1, 4),
+ RK_PINDRIVE(1, 1, 0x214, 2, 8),
+ RK_PINDRIVE(1, 1, 0x214, 3, 12),
- RK_PINDRIVE(1, 2, 0x218, 0, 2)
- RK_PINDRIVE(1, 2, 0x218, 1, 4)
- RK_PINDRIVE(1, 2, 0x218, 2, 8)
- RK_PINDRIVE(1, 2, 0x218, 3, 12)
+ RK_PINDRIVE(1, 2, 0x218, 0, 2),
+ RK_PINDRIVE(1, 2, 0x218, 1, 4),
+ RK_PINDRIVE(1, 2, 0x218, 2, 8),
+ RK_PINDRIVE(1, 2, 0x218, 3, 12),
- RK_PINDRIVE(1, 3, 0x21C, 0, 2)
- RK_PINDRIVE(1, 3, 0x21C, 1, 4)
- RK_PINDRIVE(1, 3, 0x21C, 2, 8)
- RK_PINDRIVE(1, 3, 0x21C, 3, 12)
+ RK_PINDRIVE(1, 3, 0x21C, 0, 2),
+ RK_PINDRIVE(1, 3, 0x21C, 1, 4),
+ RK_PINDRIVE(1, 3, 0x21C, 2, 8),
+ RK_PINDRIVE(1, 3, 0x21C, 3, 12),
- RK_PINDRIVE(2, 0, 0x220, 0, 2)
- RK_PINDRIVE(2, 0, 0x220, 1, 4)
- RK_PINDRIVE(2, 0, 0x220, 2, 8)
- RK_PINDRIVE(2, 0, 0x220, 3, 12)
+ RK_PINDRIVE(2, 0, 0x220, 0, 2),
+ RK_PINDRIVE(2, 0, 0x220, 1, 4),
+ RK_PINDRIVE(2, 0, 0x220, 2, 8),
+ RK_PINDRIVE(2, 0, 0x220, 3, 12),
- RK_PINDRIVE(2, 1, 0x224, 0, 2)
- RK_PINDRIVE(2, 1, 0x224, 1, 4)
- RK_PINDRIVE(2, 1, 0x224, 2, 8)
- RK_PINDRIVE(2, 1, 0x224, 3, 12)
+ RK_PINDRIVE(2, 1, 0x224, 0, 2),
+ RK_PINDRIVE(2, 1, 0x224, 1, 4),
+ RK_PINDRIVE(2, 1, 0x224, 2, 8),
+ RK_PINDRIVE(2, 1, 0x224, 3, 12),
- RK_PINDRIVE(2, 2, 0x228, 0, 2)
- RK_PINDRIVE(2, 2, 0x228, 1, 4)
- RK_PINDRIVE(2, 2, 0x228, 2, 8)
- RK_PINDRIVE(2, 2, 0x228, 3, 12)
+ RK_PINDRIVE(2, 2, 0x228, 0, 2),
+ RK_PINDRIVE(2, 2, 0x228, 1, 4),
+ RK_PINDRIVE(2, 2, 0x228, 2, 8),
+ RK_PINDRIVE(2, 2, 0x228, 3, 12),
- RK_PINDRIVE(2, 3, 0x22C, 0, 2)
- RK_PINDRIVE(2, 3, 0x22C, 1, 4)
- RK_PINDRIVE(2, 3, 0x22C, 2, 8)
- RK_PINDRIVE(2, 3, 0x22C, 3, 12)
+ RK_PINDRIVE(2, 3, 0x22C, 0, 2),
+ RK_PINDRIVE(2, 3, 0x22C, 1, 4),
+ RK_PINDRIVE(2, 3, 0x22C, 2, 8),
+ RK_PINDRIVE(2, 3, 0x22C, 3, 12),
- RK_PINDRIVE(3, 0, 0x230, 0, 2)
- RK_PINDRIVE(3, 0, 0x230, 1, 4)
- RK_PINDRIVE(3, 0, 0x230, 2, 8)
- RK_PINDRIVE(3, 0, 0x230, 3, 12)
+ RK_PINDRIVE(3, 0, 0x230, 0, 2),
+ RK_PINDRIVE(3, 0, 0x230, 1, 4),
+ RK_PINDRIVE(3, 0, 0x230, 2, 8),
+ RK_PINDRIVE(3, 0, 0x230, 3, 12),
- RK_PINDRIVE(3, 1, 0x234, 0, 2)
- RK_PINDRIVE(3, 1, 0x234, 1, 4)
- RK_PINDRIVE(3, 1, 0x234, 2, 8)
- RK_PINDRIVE(3, 1, 0x234, 3, 12)
+ RK_PINDRIVE(3, 1, 0x234, 0, 2),
+ RK_PINDRIVE(3, 1, 0x234, 1, 4),
+ RK_PINDRIVE(3, 1, 0x234, 2, 8),
+ RK_PINDRIVE(3, 1, 0x234, 3, 12),
- RK_PINDRIVE(3, 2, 0x238, 0, 2)
- RK_PINDRIVE(3, 2, 0x238, 1, 4)
- RK_PINDRIVE(3, 2, 0x238, 2, 8)
- RK_PINDRIVE(3, 2, 0x238, 3, 12)
+ RK_PINDRIVE(3, 2, 0x238, 0, 2),
+ RK_PINDRIVE(3, 2, 0x238, 1, 4),
+ RK_PINDRIVE(3, 2, 0x238, 2, 8),
+ RK_PINDRIVE(3, 2, 0x238, 3, 12),
- RK_PINDRIVE(3, 3, 0x23C, 0, 2)
- RK_PINDRIVE(3, 3, 0x23C, 1, 4)
- RK_PINDRIVE(3, 3, 0x23C, 2, 8)
- RK_PINDRIVE(3, 3, 0x23C, 3, 12)
+ RK_PINDRIVE(3, 3, 0x23C, 0, 2),
+ RK_PINDRIVE(3, 3, 0x23C, 1, 4),
+ RK_PINDRIVE(3, 3, 0x23C, 2, 8),
+ RK_PINDRIVE(3, 3, 0x23C, 3, 12),
};
static uint32_t
@@ -335,171 +521,83 @@ struct rk_pinctrl_conf rk3328_conf = {
.npin_fixup = nitems(rk3328_pin_fixup),
.pin_drive = rk3328_pin_drive,
.npin_drive = nitems(rk3328_pin_drive),
+ .gpio_bank = rk3328_gpio_bank,
+ .ngpio_bank = nitems(rk3328_gpio_bank),
.get_pd_offset = rk3328_get_pd_offset,
.get_syscon = rk3328_get_syscon,
};
+static struct rk_pinctrl_gpio rk3399_gpio_bank[] = {
+ RK_GPIO(0, "gpio0"),
+ RK_GPIO(1, "gpio1"),
+ RK_GPIO(2, "gpio2"),
+ RK_GPIO(3, "gpio3"),
+ RK_GPIO(4, "gpio4"),
+};
+
static struct rk_pinctrl_bank rk3399_iomux_bank[] = {
- {
- .bank_num = 0,
- .subbank_num = 0,
- .offset = 0x00,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 1,
- .offset = 0x04,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 2,
- .offset = 0x08,
- .nbits = 2,
- },
- {
- .bank_num = 0,
- .subbank_num = 3,
- .offset = 0x0c,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 0,
- .offset = 0x10,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 1,
- .offset = 0x14,
- .nbits = 2,
- },
- {
- .bank_num = 1,
- .subbank_num = 2,
- .offset = 0x18,
- .nbits = 2,
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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