-----Original Message-----
From: Emmanuel Vadot <m...@bidouilliste.com>
Date: 2019-12-03, Tuesday at 01:13
To: Ravi Pokala <rpok...@freebsd.org>
Cc: Emmanuel Vadot <m...@freebsd.org>, <src-committ...@freebsd.org>, 
<svn-src-all@freebsd.org>, <svn-src-h...@freebsd.org>
Subject: Re: svn commit: r355188 - in head/riscv: . sifive

    On Mon, 02 Dec 2019 13:36:06 -0800
    Ravi Pokala <rpok...@freebsd.org> wrote:
    
    > Hi Manu,
    > 
    > This creates a top-level "riscv" directory, but there are no other 
top-level ${TARGET} directories.
    > 
    > It looks like other *.dts and *.dtsi files live in either
    > 
    >     sys/dts/${TARGET}
    > 
    > or
    > 
    >     sys/gnu/dts/${TARGET}/(vendor/)?
    > 
    > So perhaps these should be moved to one of those directories, as 
appropriate?
    > 
    > Thanks,
    > 
    > Ravi (rpokala@)
    
     Thanks, I don't know how I didn't see that ... fixed with revert +
    r355324.

Thank you!

-Ravi (rpokala@)
    
    > ?-----Original Message-----
    > From: <owner-src-committ...@freebsd.org> on behalf of Emmanuel Vadot 
<m...@freebsd.org>
    > Date: 2019-11-28, Thursday at 11:38
    > To: <src-committ...@freebsd.org>, <svn-src-all@freebsd.org>, 
<svn-src-h...@freebsd.org>
    > Subject: svn commit: r355188 - in head/riscv: . sifive
    > 
    >     Author: manu
    >     Date: Thu Nov 28 19:38:57 2019
    >     New Revision: 355188
    >     URL: https://svnweb.freebsd.org/changeset/base/355188
    >     
    >     Log:
    >       Import riscv DTS files
    >       
    >       Requested by: mhorne
    >     
    >     Added:
    >       head/riscv/
    >          - copied from r355184, vendor/device-tree/dist/src/riscv/
    >     Replaced:
    >       head/riscv/sifive/fu540-c000.dtsi
    >          - copied unchanged from r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi
    >       head/riscv/sifive/hifive-unleashed-a00.dts
    >          - copied unchanged from r355185, 
vendor/device-tree/dist/src/riscv/sifive/hifive-unleashed-a00.dts
    >     
    >     Copied: head/riscv/sifive/fu540-c000.dtsi (from r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
    >     
==============================================================================
    >     --- /dev/null 00:00:00 1970   (empty, because file is newly added)
    >     +++ head/riscv/sifive/fu540-c000.dtsi Thu Nov 28 19:38:57 2019        
(r355188, copy of r355185, 
vendor/device-tree/dist/src/riscv/sifive/fu540-c000.dtsi)
    >     @@ -0,0 +1,251 @@
    >     +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
    >     +/* Copyright (c) 2018-2019 SiFive, Inc */
    >     +
    >     +/dts-v1/;
    >     +
    >     +#include <dt-bindings/clock/sifive-fu540-prci.h>
    >     +
    >     +/ {
    >     +     #address-cells = <2>;
    >     +     #size-cells = <2>;
    >     +     compatible = "sifive,fu540-c000", "sifive,fu540";
    >     +
    >     +     aliases {
    >     +             serial0 = &uart0;
    >     +             serial1 = &uart1;
    >     +             ethernet0 = &eth0;
    >     +     };
    >     +
    >     +     chosen {
    >     +     };
    >     +
    >     +     cpus {
    >     +             #address-cells = <1>;
    >     +             #size-cells = <0>;
    >     +             cpu0: cpu@0 {
    >     +                     compatible = "sifive,e51", "sifive,rocket0", 
"riscv";
    >     +                     device_type = "cpu";
    >     +                     i-cache-block-size = <64>;
    >     +                     i-cache-sets = <128>;
    >     +                     i-cache-size = <16384>;
    >     +                     reg = <0>;
    >     +                     riscv,isa = "rv64imac";
    >     +                     status = "disabled";
    >     +                     cpu0_intc: interrupt-controller {
    >     +                             #interrupt-cells = <1>;
    >     +                             compatible = "riscv,cpu-intc";
    >     +                             interrupt-controller;
    >     +                     };
    >     +             };
    >     +             cpu1: cpu@1 {
    >     +                     compatible = "sifive,u54-mc", "sifive,rocket0", 
"riscv";
    >     +                     d-cache-block-size = <64>;
    >     +                     d-cache-sets = <64>;
    >     +                     d-cache-size = <32768>;
    >     +                     d-tlb-sets = <1>;
    >     +                     d-tlb-size = <32>;
    >     +                     device_type = "cpu";
    >     +                     i-cache-block-size = <64>;
    >     +                     i-cache-sets = <64>;
    >     +                     i-cache-size = <32768>;
    >     +                     i-tlb-sets = <1>;
    >     +                     i-tlb-size = <32>;
    >     +                     mmu-type = "riscv,sv39";
    >     +                     reg = <1>;
    >     +                     riscv,isa = "rv64imafdc";
    >     +                     tlb-split;
    >     +                     cpu1_intc: interrupt-controller {
    >     +                             #interrupt-cells = <1>;
    >     +                             compatible = "riscv,cpu-intc";
    >     +                             interrupt-controller;
    >     +                     };
    >     +             };
    >     +             cpu2: cpu@2 {
    >     +                     compatible = "sifive,u54-mc", "sifive,rocket0", 
"riscv";
    >     +                     d-cache-block-size = <64>;
    >     +                     d-cache-sets = <64>;
    >     +                     d-cache-size = <32768>;
    >     +                     d-tlb-sets = <1>;
    >     +                     d-tlb-size = <32>;
    >     +                     device_type = "cpu";
    >     +                     i-cache-block-size = <64>;
    >     +                     i-cache-sets = <64>;
    >     +                     i-cache-size = <32768>;
    >     +                     i-tlb-sets = <1>;
    >     +                     i-tlb-size = <32>;
    >     +                     mmu-type = "riscv,sv39";
    >     +                     reg = <2>;
    >     +                     riscv,isa = "rv64imafdc";
    >     +                     tlb-split;
    >     +                     cpu2_intc: interrupt-controller {
    >     +                             #interrupt-cells = <1>;
    >     +                             compatible = "riscv,cpu-intc";
    >     +                             interrupt-controller;
    >     +                     };
    >     +             };
    >     +             cpu3: cpu@3 {
    >     +                     compatible = "sifive,u54-mc", "sifive,rocket0", 
"riscv";
    >     +                     d-cache-block-size = <64>;
    >     +                     d-cache-sets = <64>;
    >     +                     d-cache-size = <32768>;
    >     +                     d-tlb-sets = <1>;
    >     +                     d-tlb-size = <32>;
    >     +                     device_type = "cpu";
    >     +                     i-cache-block-size = <64>;
    >     +                     i-cache-sets = <64>;
    >     +                     i-cache-size = <32768>;
    >     +                     i-tlb-sets = <1>;
    >     +                     i-tlb-size = <32>;
    >     +                     mmu-type = "riscv,sv39";
    >     +                     reg = <3>;
    >     +                     riscv,isa = "rv64imafdc";
    >     +                     tlb-split;
    >     +                     cpu3_intc: interrupt-controller {
    >     +                             #interrupt-cells = <1>;
    >     +                             compatible = "riscv,cpu-intc";
    >     +                             interrupt-controller;
    >     +                     };
    >     +             };
    >     +             cpu4: cpu@4 {
    >     +                     compatible = "sifive,u54-mc", "sifive,rocket0", 
"riscv";
    >     +                     d-cache-block-size = <64>;
    >     +                     d-cache-sets = <64>;
    >     +                     d-cache-size = <32768>;
    >     +                     d-tlb-sets = <1>;
    >     +                     d-tlb-size = <32>;
    >     +                     device_type = "cpu";
    >     +                     i-cache-block-size = <64>;
    >     +                     i-cache-sets = <64>;
    >     +                     i-cache-size = <32768>;
    >     +                     i-tlb-sets = <1>;
    >     +                     i-tlb-size = <32>;
    >     +                     mmu-type = "riscv,sv39";
    >     +                     reg = <4>;
    >     +                     riscv,isa = "rv64imafdc";
    >     +                     tlb-split;
    >     +                     cpu4_intc: interrupt-controller {
    >     +                             #interrupt-cells = <1>;
    >     +                             compatible = "riscv,cpu-intc";
    >     +                             interrupt-controller;
    >     +                     };
    >     +             };
    >     +     };
    >     +     soc {
    >     +             #address-cells = <2>;
    >     +             #size-cells = <2>;
    >     +             compatible = "sifive,fu540-c000", "sifive,fu540", 
"simple-bus";
    >     +             ranges;
    >     +             plic0: interrupt-controller@c000000 {
    >     +                     #interrupt-cells = <1>;
    >     +                     compatible = "sifive,plic-1.0.0";
    >     +                     reg = <0x0 0xc000000 0x0 0x4000000>;
    >     +                     riscv,ndev = <53>;
    >     +                     interrupt-controller;
    >     +                     interrupts-extended = <
    >     +                             &cpu0_intc 0xffffffff
    >     +                             &cpu1_intc 0xffffffff &cpu1_intc 9
    >     +                             &cpu2_intc 0xffffffff &cpu2_intc 9
    >     +                             &cpu3_intc 0xffffffff &cpu3_intc 9
    >     +                             &cpu4_intc 0xffffffff &cpu4_intc 9>;
    >     +             };
    >     +             prci: clock-controller@10000000 {
    >     +                     compatible = "sifive,fu540-c000-prci";
    >     +                     reg = <0x0 0x10000000 0x0 0x1000>;
    >     +                     clocks = <&hfclk>, <&rtcclk>;
    >     +                     #clock-cells = <1>;
    >     +             };
    >     +             uart0: serial@10010000 {
    >     +                     compatible = "sifive,fu540-c000-uart", 
"sifive,uart0";
    >     +                     reg = <0x0 0x10010000 0x0 0x1000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <4>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     status = "disabled";
    >     +             };
    >     +             uart1: serial@10011000 {
    >     +                     compatible = "sifive,fu540-c000-uart", 
"sifive,uart0";
    >     +                     reg = <0x0 0x10011000 0x0 0x1000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <5>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     status = "disabled";
    >     +             };
    >     +             i2c0: i2c@10030000 {
    >     +                     compatible = "sifive,fu540-c000-i2c", 
"sifive,i2c0";
    >     +                     reg = <0x0 0x10030000 0x0 0x1000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <50>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     reg-shift = <2>;
    >     +                     reg-io-width = <1>;
    >     +                     #address-cells = <1>;
    >     +                     #size-cells = <0>;
    >     +                     status = "disabled";
    >     +             };
    >     +             qspi0: spi@10040000 {
    >     +                     compatible = "sifive,fu540-c000-spi", 
"sifive,spi0";
    >     +                     reg = <0x0 0x10040000 0x0 0x1000
    >     +                            0x0 0x20000000 0x0 0x10000000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <51>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     #address-cells = <1>;
    >     +                     #size-cells = <0>;
    >     +                     status = "disabled";
    >     +             };
    >     +             qspi1: spi@10041000 {
    >     +                     compatible = "sifive,fu540-c000-spi", 
"sifive,spi0";
    >     +                     reg = <0x0 0x10041000 0x0 0x1000
    >     +                            0x0 0x30000000 0x0 0x10000000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <52>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     #address-cells = <1>;
    >     +                     #size-cells = <0>;
    >     +                     status = "disabled";
    >     +             };
    >     +             qspi2: spi@10050000 {
    >     +                     compatible = "sifive,fu540-c000-spi", 
"sifive,spi0";
    >     +                     reg = <0x0 0x10050000 0x0 0x1000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <6>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     #address-cells = <1>;
    >     +                     #size-cells = <0>;
    >     +                     status = "disabled";
    >     +             };
    >     +             eth0: ethernet@10090000 {
    >     +                     compatible = "sifive,fu540-c000-gem";
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <53>;
    >     +                     reg = <0x0 0x10090000 0x0 0x2000
    >     +                            0x0 0x100a0000 0x0 0x1000>;
    >     +                     local-mac-address = [00 00 00 00 00 00];
    >     +                     clock-names = "pclk", "hclk";
    >     +                     clocks = <&prci PRCI_CLK_GEMGXLPLL>,
    >     +                              <&prci PRCI_CLK_GEMGXLPLL>;
    >     +                     #address-cells = <1>;
    >     +                     #size-cells = <0>;
    >     +                     status = "disabled";
    >     +             };
    >     +             pwm0: pwm@10020000 {
    >     +                     compatible = "sifive,fu540-c000-pwm", 
"sifive,pwm0";
    >     +                     reg = <0x0 0x10020000 0x0 0x1000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <42 43 44 45>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     #pwm-cells = <3>;
    >     +                     status = "disabled";
    >     +             };
    >     +             pwm1: pwm@10021000 {
    >     +                     compatible = "sifive,fu540-c000-pwm", 
"sifive,pwm0";
    >     +                     reg = <0x0 0x10021000 0x0 0x1000>;
    >     +                     interrupt-parent = <&plic0>;
    >     +                     interrupts = <46 47 48 49>;
    >     +                     clocks = <&prci PRCI_CLK_TLCLK>;
    >     +                     #pwm-cells = <3>;
    >     +                     status = "disabled";
    >     +             };
    >     +
    >     +     };
    >     +};
    >     
    >     Copied: head/riscv/sifive/hifive-unleashed-a00.dts (from r355185, 
vendor/device-tree/dist/src/riscv/sifive/hifive-unleashed-a00.dts)
    >     
==============================================================================
    >     --- /dev/null 00:00:00 1970   (empty, because file is newly added)
    >     +++ head/riscv/sifive/hifive-unleashed-a00.dts        Thu Nov 28 
19:38:57 2019        (r355188, copy of r355185, 
vendor/device-tree/dist/src/riscv/sifive/hifive-unleashed-a00.dts)
    >     @@ -0,0 +1,96 @@
    >     +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
    >     +/* Copyright (c) 2018-2019 SiFive, Inc */
    >     +
    >     +#include "fu540-c000.dtsi"
    >     +
    >     +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
    >     +#define RTCCLK_FREQ          1000000
    >     +
    >     +/ {
    >     +     #address-cells = <2>;
    >     +     #size-cells = <2>;
    >     +     model = "SiFive HiFive Unleashed A00";
    >     +     compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
    >     +
    >     +     chosen {
    >     +             stdout-path = "serial0";
    >     +     };
    >     +
    >     +     cpus {
    >     +             timebase-frequency = <RTCCLK_FREQ>;
    >     +     };
    >     +
    >     +     memory@80000000 {
    >     +             device_type = "memory";
    >     +             reg = <0x0 0x80000000 0x2 0x00000000>;
    >     +     };
    >     +
    >     +     soc {
    >     +     };
    >     +
    >     +     hfclk: hfclk {
    >     +             #clock-cells = <0>;
    >     +             compatible = "fixed-clock";
    >     +             clock-frequency = <33333333>;
    >     +             clock-output-names = "hfclk";
    >     +     };
    >     +
    >     +     rtcclk: rtcclk {
    >     +             #clock-cells = <0>;
    >     +             compatible = "fixed-clock";
    >     +             clock-frequency = <RTCCLK_FREQ>;
    >     +             clock-output-names = "rtcclk";
    >     +     };
    >     +};
    >     +
    >     +&uart0 {
    >     +     status = "okay";
    >     +};
    >     +
    >     +&uart1 {
    >     +     status = "okay";
    >     +};
    >     +
    >     +&i2c0 {
    >     +     status = "okay";
    >     +};
    >     +
    >     +&qspi0 {
    >     +     status = "okay";
    >     +     flash@0 {
    >     +             compatible = "issi,is25wp256", "jedec,spi-nor";
    >     +             reg = <0>;
    >     +             spi-max-frequency = <50000000>;
    >     +             m25p,fast-read;
    >     +             spi-tx-bus-width = <4>;
    >     +             spi-rx-bus-width = <4>;
    >     +     };
    >     +};
    >     +
    >     +&qspi2 {
    >     +     status = "okay";
    >     +     mmc@0 {
    >     +             compatible = "mmc-spi-slot";
    >     +             reg = <0>;
    >     +             spi-max-frequency = <20000000>;
    >     +             voltage-ranges = <3300 3300>;
    >     +             disable-wp;
    >     +     };
    >     +};
    >     +
    >     +&eth0 {
    >     +     status = "okay";
    >     +     phy-mode = "gmii";
    >     +     phy-handle = <&phy0>;
    >     +     phy0: ethernet-phy@0 {
    >     +             reg = <0>;
    >     +     };
    >     +};
    >     +
    >     +&pwm0 {
    >     +     status = "okay";
    >     +};
    >     +
    >     +&pwm1 {
    >     +     status = "okay";
    >     +};
    >     
    
    
    -- 
    Emmanuel Vadot <m...@bidouilliste.com> <m...@freebsd.org>
    


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