Author: emaste
Date: Wed Dec 11 22:09:22 2019
New Revision: 355630
URL: https://svnweb.freebsd.org/changeset/base/355630
Log:
libpmc: convert arm64 data files to proper json
jevents includes a very permissive json parser that accepts invalid
json, of which there are many examples in libpmc (typically extra or
missing commas). Convert the arm64 files to proper json so other tools
can parse them.
Sponsored by: The FreeBSD Foundation
Modified:
head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/branch.json
head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/bus.json
head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/other.json
head/lib/libpmc/pmu-events/arch/arm64/armv8-recommended.json
head/lib/libpmc/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
head/lib/libpmc/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
Modified: head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/branch.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/branch.json Wed Dec
11 19:40:30 2019 (r355629)
+++ head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/branch.json Wed Dec
11 22:09:22 2019 (r355630)
@@ -1,6 +1,6 @@
[
{
- "ArchStdEvent": "BR_INDIRECT_SPEC",
+ "ArchStdEvent": "BR_INDIRECT_SPEC"
},
{
"EventCode": "0xC9",
Modified: head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/bus.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/bus.json Wed Dec
11 19:40:30 2019 (r355629)
+++ head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/bus.json Wed Dec
11 22:09:22 2019 (r355630)
@@ -1,8 +1,8 @@
[
{
- "ArchStdEvent": "BUS_ACCESS_RD",
+ "ArchStdEvent": "BUS_ACCESS_RD"
},
{
- "ArchStdEvent": "BUS_ACCESS_WR",
+ "ArchStdEvent": "BUS_ACCESS_WR"
}
]
Modified: head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/other.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/other.json Wed Dec
11 19:40:30 2019 (r355629)
+++ head/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a53/other.json Wed Dec
11 22:09:22 2019 (r355630)
@@ -1,9 +1,9 @@
[
{
- "ArchStdEvent": "EXC_IRQ",
+ "ArchStdEvent": "EXC_IRQ"
},
{
- "ArchStdEvent": "EXC_FIQ",
+ "ArchStdEvent": "EXC_FIQ"
},
{
"EventCode": "0xC6",
Modified: head/lib/libpmc/pmu-events/arch/arm64/armv8-recommended.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/arm64/armv8-recommended.json Wed Dec
11 19:40:30 2019 (r355629)
+++ head/lib/libpmc/pmu-events/arch/arm64/armv8-recommended.json Wed Dec
11 22:09:22 2019 (r355630)
@@ -154,297 +154,297 @@
"EventCode": "0x61",
"EventName": "BUS_ACCESS_WR",
"BriefDescription": "Bus access write"
- }
+ },
{
"PublicDescription": "Bus access, Normal, Cacheable, Shareable",
"EventCode": "0x62",
"EventName": "BUS_ACCESS_SHARED",
"BriefDescription": "Bus access, Normal, Cacheable, Shareable"
- }
+ },
{
"PublicDescription": "Bus access, not Normal, Cacheable, Shareable",
"EventCode": "0x63",
"EventName": "BUS_ACCESS_NOT_SHARED",
"BriefDescription": "Bus access, not Normal, Cacheable, Shareable"
- }
+ },
{
"PublicDescription": "Bus access, Normal",
"EventCode": "0x64",
"EventName": "BUS_ACCESS_NORMAL",
"BriefDescription": "Bus access, Normal"
- }
+ },
{
"PublicDescription": "Bus access, peripheral",
"EventCode": "0x65",
"EventName": "BUS_ACCESS_PERIPH",
"BriefDescription": "Bus access, peripheral"
- }
+ },
{
"PublicDescription": "Data memory access, read",
"EventCode": "0x66",
"EventName": "MEM_ACCESS_RD",
"BriefDescription": "Data memory access, read"
- }
+ },
{
"PublicDescription": "Data memory access, write",
"EventCode": "0x67",
"EventName": "MEM_ACCESS_WR",
"BriefDescription": "Data memory access, write"
- }
+ },
{
"PublicDescription": "Unaligned access, read",
"EventCode": "0x68",
"EventName": "UNALIGNED_LD_SPEC",
"BriefDescription": "Unaligned access, read"
- }
+ },
{
"PublicDescription": "Unaligned access, write",
"EventCode": "0x69",
"EventName": "UNALIGNED_ST_SPEC",
"BriefDescription": "Unaligned access, write"
- }
+ },
{
"PublicDescription": "Unaligned access",
"EventCode": "0x6a",
"EventName": "UNALIGNED_LDST_SPEC",
"BriefDescription": "Unaligned access"
- }
+ },
{
"PublicDescription": "Exclusive operation speculatively executed,
LDREX or LDX",
"EventCode": "0x6c",
"EventName": "LDREX_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, LDREX
or LDX"
- }
+ },
{
"PublicDescription": "Exclusive operation speculatively executed,
STREX or STX pass",
"EventCode": "0x6d",
"EventName": "STREX_PASS_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX
or STX pass"
- }
+ },
{
"PublicDescription": "Exclusive operation speculatively executed,
STREX or STX fail",
"EventCode": "0x6e",
"EventName": "STREX_FAIL_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX
or STX fail"
- }
+ },
{
"PublicDescription": "Exclusive operation speculatively executed,
STREX or STX",
"EventCode": "0x6f",
"EventName": "STREX_SPEC",
"BriefDescription": "Exclusive operation speculatively executed, STREX
or STX"
- }
+ },
{
"PublicDescription": "Operation speculatively executed, load",
"EventCode": "0x70",
"EventName": "LD_SPEC",
"BriefDescription": "Operation speculatively executed, load"
- }
+ },
{
- "PublicDescription": "Operation speculatively executed, store"
+ "PublicDescription": "Operation speculatively executed, store",
"EventCode": "0x71",
"EventName": "ST_SPEC",
"BriefDescription": "Operation speculatively executed, store"
- }
+ },
{
"PublicDescription": "Operation speculatively executed, load or store",
"EventCode": "0x72",
"EventName": "LDST_SPEC",
"BriefDescription": "Operation speculatively executed, load or store"
- }
+ },
{
"PublicDescription": "Operation speculatively executed, integer data
processing",
"EventCode": "0x73",
"EventName": "DP_SPEC",
"BriefDescription": "Operation speculatively executed, integer data
processing"
- }
+ },
{
"PublicDescription": "Operation speculatively executed, Advanced SIMD
instruction",
"EventCode": "0x74",
"EventName": "ASE_SPEC",
- "BriefDescription": "Operation speculatively executed, Advanced SIMD
instruction",
- }
+ "BriefDescription": "Operation speculatively executed, Advanced SIMD
instruction"
+ },
{
"PublicDescription": "Operation speculatively executed, floating-point
instruction",
"EventCode": "0x75",
"EventName": "VFP_SPEC",
"BriefDescription": "Operation speculatively executed, floating-point
instruction"
- }
+ },
{
"PublicDescription": "Operation speculatively executed, software
change of the PC",
"EventCode": "0x76",
"EventName": "PC_WRITE_SPEC",
"BriefDescription": "Operation speculatively executed, software change
of the PC"
- }
+ },
{
"PublicDescription": "Operation speculatively executed, Cryptographic
instruction",
"EventCode": "0x77",
"EventName": "CRYPTO_SPEC",
"BriefDescription": "Operation speculatively executed, Cryptographic
instruction"
- }
+ },
{
- "PublicDescription": "Branch speculatively executed, immediate branch"
+ "PublicDescription": "Branch speculatively executed, immediate branch",
"EventCode": "0x78",
"EventName": "BR_IMMED_SPEC",
"BriefDescription": "Branch speculatively executed, immediate branch"
- }
+ },
{
- "PublicDescription": "Branch speculatively executed, procedure return"
+ "PublicDescription": "Branch speculatively executed, procedure return",
"EventCode": "0x79",
"EventName": "BR_RETURN_SPEC",
"BriefDescription": "Branch speculatively executed, procedure return"
- }
+ },
{
- "PublicDescription": "Branch speculatively executed, indirect branch"
+ "PublicDescription": "Branch speculatively executed, indirect branch",
"EventCode": "0x7a",
"EventName": "BR_INDIRECT_SPEC",
"BriefDescription": "Branch speculatively executed, indirect branch"
- }
+ },
{
- "PublicDescription": "Barrier speculatively executed, ISB"
+ "PublicDescription": "Barrier speculatively executed, ISB",
"EventCode": "0x7c",
"EventName": "ISB_SPEC",
"BriefDescription": "Barrier speculatively executed, ISB"
- }
+ },
{
- "PublicDescription": "Barrier speculatively executed, DSB"
+ "PublicDescription": "Barrier speculatively executed, DSB",
"EventCode": "0x7d",
"EventName": "DSB_SPEC",
"BriefDescription": "Barrier speculatively executed, DSB"
- }
+ },
{
- "PublicDescription": "Barrier speculatively executed, DMB"
+ "PublicDescription": "Barrier speculatively executed, DMB",
"EventCode": "0x7e",
"EventName": "DMB_SPEC",
"BriefDescription": "Barrier speculatively executed, DMB"
- }
+ },
{
- "PublicDescription": "Exception taken, Other synchronous"
+ "PublicDescription": "Exception taken, Other synchronous",
"EventCode": "0x81",
"EventName": "EXC_UNDEF",
"BriefDescription": "Exception taken, Other synchronous"
- }
+ },
{
- "PublicDescription": "Exception taken, Supervisor Call"
+ "PublicDescription": "Exception taken, Supervisor Call",
"EventCode": "0x82",
"EventName": "EXC_SVC",
"BriefDescription": "Exception taken, Supervisor Call"
- }
+ },
{
- "PublicDescription": "Exception taken, Instruction Abort"
+ "PublicDescription": "Exception taken, Instruction Abort",
"EventCode": "0x83",
"EventName": "EXC_PABORT",
"BriefDescription": "Exception taken, Instruction Abort"
- }
+ },
{
- "PublicDescription": "Exception taken, Data Abort and SError"
+ "PublicDescription": "Exception taken, Data Abort and SError",
"EventCode": "0x84",
"EventName": "EXC_DABORT",
"BriefDescription": "Exception taken, Data Abort and SError"
- }
+ },
{
- "PublicDescription": "Exception taken, IRQ"
+ "PublicDescription": "Exception taken, IRQ",
"EventCode": "0x86",
"EventName": "EXC_IRQ",
"BriefDescription": "Exception taken, IRQ"
- }
+ },
{
- "PublicDescription": "Exception taken, FIQ"
+ "PublicDescription": "Exception taken, FIQ",
"EventCode": "0x87",
"EventName": "EXC_FIQ",
"BriefDescription": "Exception taken, FIQ"
- }
+ },
{
- "PublicDescription": "Exception taken, Secure Monitor Call"
+ "PublicDescription": "Exception taken, Secure Monitor Call",
"EventCode": "0x88",
"EventName": "EXC_SMC",
"BriefDescription": "Exception taken, Secure Monitor Call"
- }
+ },
{
- "PublicDescription": "Exception taken, Hypervisor Call"
+ "PublicDescription": "Exception taken, Hypervisor Call",
"EventCode": "0x8a",
"EventName": "EXC_HVC",
"BriefDescription": "Exception taken, Hypervisor Call"
- }
+ },
{
- "PublicDescription": "Exception taken, Instruction Abort not taken
locally"
+ "PublicDescription": "Exception taken, Instruction Abort not taken
locally",
"EventCode": "0x8b",
"EventName": "EXC_TRAP_PABORT",
"BriefDescription": "Exception taken, Instruction Abort not taken
locally"
- }
+ },
{
- "PublicDescription": "Exception taken, Data Abort or SError not taken
locally"
+ "PublicDescription": "Exception taken, Data Abort or SError not taken
locally",
"EventCode": "0x8c",
"EventName": "EXC_TRAP_DABORT",
"BriefDescription": "Exception taken, Data Abort or SError not taken
locally"
- }
+ },
{
- "PublicDescription": "Exception taken, Other traps not taken locally"
+ "PublicDescription": "Exception taken, Other traps not taken locally",
"EventCode": "0x8d",
"EventName": "EXC_TRAP_OTHER",
"BriefDescription": "Exception taken, Other traps not taken locally"
- }
+ },
{
- "PublicDescription": "Exception taken, IRQ not taken locally"
+ "PublicDescription": "Exception taken, IRQ not taken locally",
"EventCode": "0x8e",
"EventName": "EXC_TRAP_IRQ",
"BriefDescription": "Exception taken, IRQ not taken locally"
- }
+ },
{
- "PublicDescription": "Exception taken, FIQ not taken locally"
+ "PublicDescription": "Exception taken, FIQ not taken locally",
"EventCode": "0x8f",
"EventName": "EXC_TRAP_FIQ",
"BriefDescription": "Exception taken, FIQ not taken locally"
- }
+ },
{
- "PublicDescription": "Release consistency operation speculatively
executed, Load-Acquire"
+ "PublicDescription": "Release consistency operation speculatively
executed, Load-Acquire",
"EventCode": "0x90",
"EventName": "RC_LD_SPEC",
"BriefDescription": "Release consistency operation speculatively
executed, Load-Acquire"
- }
+ },
{
- "PublicDescription": "Release consistency operation speculatively
executed, Store-Release"
+ "PublicDescription": "Release consistency operation speculatively
executed, Store-Release",
"EventCode": "0x91",
"EventName": "RC_ST_SPEC",
"BriefDescription": "Release consistency operation speculatively
executed, Store-Release"
- }
+ },
{
- "PublicDescription": "Attributable Level 3 data or unified cache
access, read"
+ "PublicDescription": "Attributable Level 3 data or unified cache
access, read",
"EventCode": "0xa0",
"EventName": "L3D_CACHE_RD",
"BriefDescription": "Attributable Level 3 data or unified cache
access, read"
- }
+ },
{
- "PublicDescription": "Attributable Level 3 data or unified cache
access, write"
+ "PublicDescription": "Attributable Level 3 data or unified cache
access, write",
"EventCode": "0xa1",
"EventName": "L3D_CACHE_WR",
"BriefDescription": "Attributable Level 3 data or unified cache
access, write"
- }
+ },
{
- "PublicDescription": "Attributable Level 3 data or unified cache
refill, read"
+ "PublicDescription": "Attributable Level 3 data or unified cache
refill, read",
"EventCode": "0xa2",
"EventName": "L3D_CACHE_REFILL_RD",
"BriefDescription": "Attributable Level 3 data or unified cache
refill, read"
- }
+ },
{
- "PublicDescription": "Attributable Level 3 data or unified cache
refill, write"
+ "PublicDescription": "Attributable Level 3 data or unified cache
refill, write",
"EventCode": "0xa3",
"EventName": "L3D_CACHE_REFILL_WR",
"BriefDescription": "Attributable Level 3 data or unified cache
refill, write"
- }
+ },
{
- "PublicDescription": "Attributable Level 3 data or unified cache
Write-Back, victim"
+ "PublicDescription": "Attributable Level 3 data or unified cache
Write-Back, victim",
"EventCode": "0xa6",
"EventName": "L3D_CACHE_WB_VICTIM",
"BriefDescription": "Attributable Level 3 data or unified cache
Write-Back, victim"
- }
+ },
{
- "PublicDescription": "Attributable Level 3 data or unified cache
Write-Back, cache clean"
+ "PublicDescription": "Attributable Level 3 data or unified cache
Write-Back, cache clean",
"EventCode": "0xa7",
"EventName": "L3D_CACHE_WB_CLEAN",
"BriefDescription": "Attributable Level 3 data or unified cache
Write-Back, cache clean"
- }
+ },
{
- "PublicDescription": "Attributable Level 3 data or unified cache
access, invalidate"
+ "PublicDescription": "Attributable Level 3 data or unified cache
access, invalidate",
"EventCode": "0xa8",
"EventName": "L3D_CACHE_INVAL",
"BriefDescription": "Attributable Level 3 data or unified cache
access, invalidate"
Modified:
head/lib/libpmc/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
Wed Dec 11 19:40:30 2019 (r355629)
+++ head/lib/libpmc/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
Wed Dec 11 22:09:22 2019 (r355630)
@@ -1,32 +1,32 @@
[
{
- "ArchStdEvent": "L1D_CACHE_RD",
+ "ArchStdEvent": "L1D_CACHE_RD"
},
{
- "ArchStdEvent": "L1D_CACHE_WR",
+ "ArchStdEvent": "L1D_CACHE_WR"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
- "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
- "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
- "ArchStdEvent": "L1D_TLB_RD",
+ "ArchStdEvent": "L1D_TLB_RD"
},
{
- "ArchStdEvent": "L1D_TLB_WR",
+ "ArchStdEvent": "L1D_TLB_WR"
},
{
- "ArchStdEvent": "BUS_ACCESS_RD",
+ "ArchStdEvent": "BUS_ACCESS_RD"
},
{
- "ArchStdEvent": "BUS_ACCESS_WR",
+ "ArchStdEvent": "BUS_ACCESS_WR"
}
]
Modified:
head/lib/libpmc/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
==============================================================================
--- head/lib/libpmc/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
Wed Dec 11 19:40:30 2019 (r355629)
+++ head/lib/libpmc/pmu-events/arch/arm64/hisilicon/hip08/core-imp-def.json
Wed Dec 11 22:09:22 2019 (r355630)
@@ -1,122 +1,122 @@
[
{
- "ArchStdEvent": "L1D_CACHE_RD",
+ "ArchStdEvent": "L1D_CACHE_RD"
},
{
- "ArchStdEvent": "L1D_CACHE_WR",
+ "ArchStdEvent": "L1D_CACHE_WR"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
- "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
},
{
- "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
},
{
- "ArchStdEvent": "L1D_CACHE_INVAL",
+ "ArchStdEvent": "L1D_CACHE_INVAL"
},
{
- "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
- "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
- "ArchStdEvent": "L1D_TLB_RD",
+ "ArchStdEvent": "L1D_TLB_RD"
},
{
- "ArchStdEvent": "L1D_TLB_WR",
+ "ArchStdEvent": "L1D_TLB_WR"
},
{
- "ArchStdEvent": "L2D_CACHE_RD",
+ "ArchStdEvent": "L2D_CACHE_RD"
},
{
- "ArchStdEvent": "L2D_CACHE_WR",
+ "ArchStdEvent": "L2D_CACHE_WR"
},
{
- "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD"
},
{
- "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR"
},
{
- "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
},
{
- "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
},
{
- "ArchStdEvent": "L2D_CACHE_INVAL",
+ "ArchStdEvent": "L2D_CACHE_INVAL"
},
{
"PublicDescription": "Level 1 instruction cache prefetch access count",
"EventCode": "0x102e",
"EventName": "L1I_CACHE_PRF",
- "BriefDescription": "L1I cache prefetch access count",
+ "BriefDescription": "L1I cache prefetch access count"
},
{
"PublicDescription": "Level 1 instruction cache miss due to prefetch
access count",
"EventCode": "0x102f",
"EventName": "L1I_CACHE_PRF_REFILL",
- "BriefDescription": "L1I cache miss due to prefetch access count",
+ "BriefDescription": "L1I cache miss due to prefetch access count"
},
{
"PublicDescription": "Instruction queue is empty",
"EventCode": "0x1043",
"EventName": "IQ_IS_EMPTY",
- "BriefDescription": "Instruction queue is empty",
+ "BriefDescription": "Instruction queue is empty"
},
{
"PublicDescription": "Instruction fetch stall cycles",
"EventCode": "0x1044",
"EventName": "IF_IS_STALL",
- "BriefDescription": "Instruction fetch stall cycles",
+ "BriefDescription": "Instruction fetch stall cycles"
},
{
"PublicDescription": "Instructions can receive, but not send",
"EventCode": "0x2014",
"EventName": "FETCH_BUBBLE",
- "BriefDescription": "Instructions can receive, but not send",
+ "BriefDescription": "Instructions can receive, but not send"
},
{
"PublicDescription": "Prefetch request from LSU",
"EventCode": "0x6013",
"EventName": "PRF_REQ",
- "BriefDescription": "Prefetch request from LSU",
+ "BriefDescription": "Prefetch request from LSU"
},
{
"PublicDescription": "Hit on prefetched data",
"EventCode": "0x6014",
"EventName": "HIT_ON_PRF",
- "BriefDescription": "Hit on prefetched data",
+ "BriefDescription": "Hit on prefetched data"
},
{
"PublicDescription": "Cycles of that the number of issuing micro
operations are less than 4",
"EventCode": "0x7001",
"EventName": "EXE_STALL_CYCLE",
- "BriefDescription": "Cycles of that the number of issue ups are less
than 4",
+ "BriefDescription": "Cycles of that the number of issue ups are less
than 4"
},
{
"PublicDescription": "No any micro operation is issued and meanwhile
any load operation is not resolved",
"EventCode": "0x7004",
"EventName": "MEM_STALL_ANYLOAD",
- "BriefDescription": "No any micro operation is issued and meanwhile
any load operation is not resolved",
+ "BriefDescription": "No any micro operation is issued and meanwhile
any load operation is not resolved"
},
{
"PublicDescription": "No any micro operation is issued and meanwhile
there is any load operation missing L1 cache and pending data refill",
"EventCode": "0x7006",
"EventName": "MEM_STALL_L1MISS",
- "BriefDescription": "No any micro operation is issued and meanwhile
there is any load operation missing L1 cache and pending data refill",
+ "BriefDescription": "No any micro operation is issued and meanwhile
there is any load operation missing L1 cache and pending data refill"
},
{
"PublicDescription": "No any micro operation is issued and meanwhile
there is any load operation missing both L1 and L2 cache and pending data
refill from L3 cache",
"EventCode": "0x7007",
"EventName": "MEM_STALL_L2MISS",
- "BriefDescription": "No any micro operation is issued and meanwhile
there is any load operation missing both L1 and L2 cache and pending data
refill from L3 cache",
- },
+ "BriefDescription": "No any micro operation is issued and meanwhile
there is any load operation missing both L1 and L2 cache and pending data
refill from L3 cache"
+ }
]
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